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[PowerPC] Simplify fp-to-int store optimization
On PowerPC VSX targets, fp-to-int will be transformed into xscv with mfvsr. When the result is to be stored, mfvsr can be replaced by a direct store. This change simplifies the optimization by using existing fp-to-int code, which helps CSE and handling strictfp cases. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D141473
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10 files changed

+362
-369
lines changed

10 files changed

+362
-369
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 18 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1642,10 +1642,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
16421642
case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
16431643
case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
16441644
case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1645-
case PPCISD::FP_TO_UINT_IN_VSR:
1646-
return "PPCISD::FP_TO_UINT_IN_VSR,";
1647-
case PPCISD::FP_TO_SINT_IN_VSR:
1648-
return "PPCISD::FP_TO_SINT_IN_VSR";
16491645
case PPCISD::FRE: return "PPCISD::FRE";
16501646
case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
16511647
case PPCISD::FTSQRT:
@@ -8117,7 +8113,11 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
81178113
// For strict nodes, source is the second operand.
81188114
SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
81198115
SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
8120-
assert(Src.getValueType().isFloatingPoint());
8116+
MVT DestTy = Op.getSimpleValueType();
8117+
assert(Src.getValueType().isFloatingPoint() &&
8118+
(DestTy == MVT::i8 || DestTy == MVT::i16 || DestTy == MVT::i32 ||
8119+
DestTy == MVT::i64) &&
8120+
"Invalid FP_TO_INT types");
81218121
if (Src.getValueType() == MVT::f32) {
81228122
if (IsStrict) {
81238123
Src =
@@ -8127,9 +8127,10 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
81278127
} else
81288128
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
81298129
}
8130-
SDValue Conv;
8130+
if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector())
8131+
DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
81318132
unsigned Opc = ISD::DELETED_NODE;
8132-
switch (Op.getSimpleValueType().SimpleTy) {
8133+
switch (DestTy.SimpleTy) {
81338134
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
81348135
case MVT::i32:
81358136
Opc = IsSigned ? PPCISD::FCTIWZ
@@ -8140,12 +8141,14 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
81408141
"i64 FP_TO_UINT is supported only with FPCVT");
81418142
Opc = IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ;
81428143
}
8144+
EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64;
8145+
SDValue Conv;
81438146
if (IsStrict) {
81448147
Opc = getPPCStrictOpcode(Opc);
8145-
Conv = DAG.getNode(Opc, dl, DAG.getVTList(MVT::f64, MVT::Other),
8146-
{Chain, Src}, Flags);
8148+
Conv = DAG.getNode(Opc, dl, DAG.getVTList(ConvTy, MVT::Other), {Chain, Src},
8149+
Flags);
81478150
} else {
8148-
Conv = DAG.getNode(Opc, dl, MVT::f64, Src);
8151+
Conv = DAG.getNode(Opc, dl, ConvTy, Src);
81498152
}
81508153
return Conv;
81518154
}
@@ -15054,30 +15057,18 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
1505415057

1505515058
// Only perform combine for conversion to i64/i32 or power9 i16/i8.
1505615059
bool ValidTypeForStoreFltAsInt =
15057-
(Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
15060+
(Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) ||
1505815061
(Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
1505915062

15060-
if (ResVT == MVT::f128 && !Subtarget.hasP9Vector())
15063+
// TODO: Lower conversion from f128 on all VSX targets
15064+
if (ResVT == MVT::ppcf128 || (ResVT == MVT::f128 && !Subtarget.hasP9Vector()))
1506115065
return SDValue();
1506215066

15063-
if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
15067+
if ((Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) ||
1506415068
cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
1506515069
return SDValue();
1506615070

15067-
// Extend f32 values to f64
15068-
if (ResVT.getScalarSizeInBits() == 32) {
15069-
Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
15070-
DCI.AddToWorklist(Val.getNode());
15071-
}
15072-
15073-
// Set signed or unsigned conversion opcode.
15074-
unsigned ConvOpcode = (Opcode == ISD::FP_TO_SINT) ?
15075-
PPCISD::FP_TO_SINT_IN_VSR :
15076-
PPCISD::FP_TO_UINT_IN_VSR;
15077-
15078-
Val = DAG.getNode(ConvOpcode,
15079-
dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, Val);
15080-
DCI.AddToWorklist(Val.getNode());
15071+
Val = convertFPToInt(N->getOperand(1), DAG, Subtarget);
1508115072

1508215073
// Set number of bytes being converted.
1508315074
unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8;
@@ -15090,7 +15081,6 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
1509015081
cast<StoreSDNode>(N)->getMemoryVT(),
1509115082
cast<StoreSDNode>(N)->getMemOperand());
1509215083

15093-
DCI.AddToWorklist(Val.getNode());
1509415084
return Val;
1509515085
}
1509615086

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -78,10 +78,6 @@ namespace llvm {
7878
FCTIDUZ,
7979
FCTIWUZ,
8080

81-
/// Floating-point-to-integer conversion instructions
82-
FP_TO_UINT_IN_VSR,
83-
FP_TO_SINT_IN_VSR,
84-
8581
/// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
8682
/// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
8783
VEXTS,

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [
3232
SDTCisFP<0>, SDTCisFP<1>
3333
]>;
3434
def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [
35-
SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
35+
SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
3636
]>;
3737
def SDT_PPCVexts : SDTypeProfile<1, 2, [
3838
SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
@@ -164,10 +164,6 @@ def PPCany_fcfidus : PatFrags<(ops node:$op),
164164
[(PPCfcfidus node:$op),
165165
(PPCstrict_fcfidus node:$op)]>;
166166

167-
def PPCcv_fp_to_uint_in_vsr:
168-
SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>;
169-
def PPCcv_fp_to_sint_in_vsr:
170-
SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>;
171167
def PPCstore_scal_int_from_vsr:
172168
SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr,
173169
[SDNPHasChain, SDNPMayStore]>;

‎llvm/lib/Target/PowerPC/PPCInstrP10.td

Lines changed: 8 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1252,23 +1252,10 @@ let Predicates = [PCRelativeMemops] in {
12521252
(PSTDpc $RS, $ga, 0)>;
12531253

12541254
// Special Cases For PPCstore_scal_int_from_vsr
1255-
def : Pat<(PPCstore_scal_int_from_vsr
1256-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)),
1257-
(PPCmatpcreladdr PCRelForm:$dst), 8),
1258-
(PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>;
1259-
def : Pat<(PPCstore_scal_int_from_vsr
1260-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)),
1261-
(PPCmatpcreladdr PCRelForm:$dst), 8),
1262-
(PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>;
1263-
1264-
def : Pat<(PPCstore_scal_int_from_vsr
1265-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)),
1266-
(PPCmatpcreladdr PCRelForm:$dst), 8),
1267-
(PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>;
1268-
def : Pat<(PPCstore_scal_int_from_vsr
1269-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
1270-
(PPCmatpcreladdr PCRelForm:$dst), 8),
1271-
(PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
1255+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1256+
(PSTXSDpc $src, $dst, 0)>;
1257+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, (PPCmatpcreladdr PCRelForm:$dst), 8),
1258+
(PSTXSDpc (COPY_TO_REGCLASS $src, VFRC), $dst, 0)>;
12721259

12731260
def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
12741261
(SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
@@ -2209,20 +2196,10 @@ def : Pat<(f64 nzFPImmAsi64:$A),
22092196
def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
22102197

22112198
// Cases For PPCstore_scal_int_from_vsr
2212-
def : Pat<(PPCstore_scal_int_from_vsr
2213-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8),
2214-
(PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>;
2215-
def : Pat<(PPCstore_scal_int_from_vsr
2216-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8),
2217-
(PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>;
2218-
def : Pat<(PPCstore_scal_int_from_vsr
2219-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8),
2220-
(PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
2221-
PDForm:$dst)>;
2222-
def : Pat<(PPCstore_scal_int_from_vsr
2223-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8),
2224-
(PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
2225-
PDForm:$dst)>;
2199+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, PDForm:$dst, 8),
2200+
(PSTXSD $src, PDForm:$dst)>;
2201+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, PDForm:$dst, 8),
2202+
(PSTXSD (COPY_TO_REGCLASS $src, VFRC), PDForm:$dst)>;
22262203
}
22272204

22282205
let Predicates = [PrefixInstrs] in {

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 38 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,10 +1486,14 @@ let Predicates = [HasVSX, HasP9Vector] in {
14861486

14871487
// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
14881488
let mayRaiseFPException = 1 in {
1489-
def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
1490-
def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
1491-
def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
1492-
def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>;
1489+
def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz",
1490+
[(set f128:$RST, (PPCany_fctidz f128:$RB))]>;
1491+
def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz",
1492+
[(set f128:$RST, (PPCany_fctiwz f128:$RB))]>;
1493+
def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz",
1494+
[(set f128:$RST, (PPCany_fctiduz f128:$RB))]>;
1495+
def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz",
1496+
[(set f128:$RST, (PPCany_fctiwuz f128:$RB))]>;
14931497
}
14941498

14951499
// Convert (Un)Signed DWord -> QP.
@@ -2909,6 +2913,10 @@ def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
29092913
def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
29102914
(COPY_TO_REGCLASS (XXMRGHW (COPY_TO_REGCLASS $vB, VSRC),
29112915
(COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
2916+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, XForm:$dst, 8),
2917+
(STXSDX $src, XForm:$dst)>;
2918+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, XForm:$dst, 8),
2919+
(STXSDX (COPY_TO_REGCLASS $src, VSFRC), XForm:$dst)>;
29122920
} // HasVSX
29132921

29142922
// Any big endian VSX subtarget.
@@ -3151,12 +3159,10 @@ def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),
31513159

31523160
// Any pre-Power9 VSX subtarget.
31533161
let Predicates = [HasVSX, NoP9Vector] in {
3154-
def : Pat<(PPCstore_scal_int_from_vsr
3155-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 8),
3156-
(STXSDX (XSCVDPSXDS f64:$src), ForceXForm:$dst)>;
3157-
def : Pat<(PPCstore_scal_int_from_vsr
3158-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 8),
3159-
(STXSDX (XSCVDPUXDS f64:$src), ForceXForm:$dst)>;
3162+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 8),
3163+
(STXSDX $src, ForceXForm:$dst)>;
3164+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8),
3165+
(STXSDX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;
31603166

31613167
// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads).
31623168
defm : ScalToVecWPermute<
@@ -3303,12 +3309,15 @@ def : Pat<(f32 (fneg f32:$S)),
33033309
(COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>;
33043310

33053311
// Instructions for converting float to i32 feeding a store.
3306-
def : Pat<(PPCstore_scal_int_from_vsr
3307-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 4),
3308-
(STIWX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
3309-
def : Pat<(PPCstore_scal_int_from_vsr
3310-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 4),
3311-
(STIWX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
3312+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4),
3313+
(STIWX $src, ForceXForm:$dst)>;
3314+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4),
3315+
(STIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;
3316+
3317+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 4),
3318+
(STXSIWX $src, ForceXForm:$dst)>;
3319+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 4),
3320+
(STXSIWX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;
33123321

33133322
def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)),
33143323
(v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC),
@@ -4042,67 +4051,19 @@ def : Pat<(i32 (any_fp_to_uint f128:$src)),
40424051
(i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
40434052

40444053
// Instructions for store(fptosi).
4045-
// The 8-byte version is repeated here due to availability of D-Form STXSD.
4046-
def : Pat<(PPCstore_scal_int_from_vsr
4047-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), XForm:$dst, 8),
4048-
(STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
4049-
XForm:$dst)>;
4050-
def : Pat<(PPCstore_scal_int_from_vsr
4051-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), DSForm:$dst, 8),
4052-
(STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
4053-
DSForm:$dst)>;
4054-
def : Pat<(PPCstore_scal_int_from_vsr
4055-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 4),
4056-
(STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4057-
def : Pat<(PPCstore_scal_int_from_vsr
4058-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 2),
4059-
(STXSIHX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4060-
def : Pat<(PPCstore_scal_int_from_vsr
4061-
(f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), ForceXForm:$dst, 1),
4062-
(STXSIBX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), ForceXForm:$dst)>;
4063-
def : Pat<(PPCstore_scal_int_from_vsr
4064-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), XForm:$dst, 8),
4065-
(STXSDX (XSCVDPSXDS f64:$src), XForm:$dst)>;
4066-
def : Pat<(PPCstore_scal_int_from_vsr
4067-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), DSForm:$dst, 8),
4068-
(STXSD (XSCVDPSXDS f64:$src), DSForm:$dst)>;
4069-
def : Pat<(PPCstore_scal_int_from_vsr
4070-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 2),
4071-
(STXSIHX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
4072-
def : Pat<(PPCstore_scal_int_from_vsr
4073-
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), ForceXForm:$dst, 1),
4074-
(STXSIBX (XSCVDPSXWS f64:$src), ForceXForm:$dst)>;
4075-
4076-
// Instructions for store(fptoui).
4077-
def : Pat<(PPCstore_scal_int_from_vsr
4078-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), XForm:$dst, 8),
4079-
(STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
4080-
XForm:$dst)>;
4081-
def : Pat<(PPCstore_scal_int_from_vsr
4082-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), DSForm:$dst, 8),
4083-
(STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
4084-
DSForm:$dst)>;
4085-
def : Pat<(PPCstore_scal_int_from_vsr
4086-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 4),
4087-
(STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4088-
def : Pat<(PPCstore_scal_int_from_vsr
4089-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 2),
4090-
(STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4091-
def : Pat<(PPCstore_scal_int_from_vsr
4092-
(f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), ForceXForm:$dst, 1),
4093-
(STXSIBX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), ForceXForm:$dst)>;
4094-
def : Pat<(PPCstore_scal_int_from_vsr
4095-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), XForm:$dst, 8),
4096-
(STXSDX (XSCVDPUXDS f64:$src), XForm:$dst)>;
4097-
def : Pat<(PPCstore_scal_int_from_vsr
4098-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), DSForm:$dst, 8),
4099-
(STXSD (XSCVDPUXDS f64:$src), DSForm:$dst)>;
4100-
def : Pat<(PPCstore_scal_int_from_vsr
4101-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 2),
4102-
(STXSIHX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
4103-
def : Pat<(PPCstore_scal_int_from_vsr
4104-
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), ForceXForm:$dst, 1),
4105-
(STXSIBX (XSCVDPUXWS f64:$src), ForceXForm:$dst)>;
4054+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, DSForm:$dst, 8),
4055+
(STXSD $src, DSForm:$dst)>;
4056+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 2),
4057+
(STXSIHX $src, ForceXForm:$dst)>;
4058+
def : Pat<(PPCstore_scal_int_from_vsr f64:$src, ForceXForm:$dst, 1),
4059+
(STXSIBX $src, ForceXForm:$dst)>;
4060+
4061+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, DSForm:$dst, 8),
4062+
(STXSD (COPY_TO_REGCLASS $src, VFRC), DSForm:$dst)>;
4063+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 2),
4064+
(STXSIHX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;
4065+
def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 1),
4066+
(STXSIBX (COPY_TO_REGCLASS $src, VSFRC), ForceXForm:$dst)>;
41064067

41074068
// Round & Convert QP -> DP/SP
41084069
def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>;

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