Skip to content

Commit 8fa32a7

Browse files
committed
[RISCV] Fix an obvious CSE opportunity in LSR test case. NFC
1 parent f9f708e commit 8fa32a7

File tree

1 file changed

+1
-2
lines changed

1 file changed

+1
-2
lines changed

llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,13 +75,12 @@ define void @test(i32 signext %i) nounwind {
7575
entry:
7676
%k_addr.012 = shl i32 %i, 1
7777
%tmp14 = icmp sgt i32 %k_addr.012, 8192
78-
%tmp. = shl i32 %i, 1
7978
br i1 %tmp14, label %return, label %bb
8079

8180
bb:
8281
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
8382
%tmp.15 = mul i32 %indvar, %i
84-
%tmp.16 = add i32 %tmp.15, %tmp.
83+
%tmp.16 = add i32 %tmp.15, %k_addr.012
8584
%gep.upgrd.1 = zext i32 %tmp.16 to i64
8685
%tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1
8786
store i8 0, i8* %tmp

0 commit comments

Comments
 (0)