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RISC-V: Support ".option [no]exact" assembler directives
This commit adds two assembler directives: ".option exact" and ".option noexact" (enable/disable the exact mode) as discussed in <riscv-non-isa/riscv-asm-manual#122> and already implemented in LLVM. When the exact mode is enabled, 1. Linker relaxations are turned off, 2. Instruction aliases that will change the encoding from the (likely non-alias) instruction with the same name are disabled (e.g. "addi" will never turn into "c.addi" even if optimizable) and 3. Assembler relaxation of branch instructions are disabled (e.g. "blt" with a long offset will not turn into "bge + j"). Macros like "li" (known to be expanded into possibly complex sequences) may still expand to complex instruction sequences but at least each instruction emitted by macros is still subject to the behavior above. Currently, interactions between ".option relax/norelax" and ".option exact/noexact" are designed to be LLVM-compatible (i.e. ".option exact/noexact" imply ".option norelax/relax", respectively) but considered flaky and strongly discouraged from using both. cf. <llvm/llvm-project#122483> gas/ChangeLog: * config/tc-riscv.c (struct riscv_set_options): Add exact option. (RELAX_BRANCH_ENCODE): Encode exact option. (RELAX_BRANCH_EXACT): New predicate macro. (relaxed_branch_length): Handle exact mode cases. (append_insn): Pass exact option to RELAX_BRANCH_ENCODE. (riscv_ip): Skip instructions that would change the encoding when the exact mode is enabled. (s_riscv_option): Parse ".option exact" and ".option noexact" assembler directives. * doc/c-riscv.texi: Document new assembler directives. * testsuite/gas/riscv/exact.s: Test exact mode basics. * testsuite/gas/riscv/exact.d: Ditto. * testsuite/gas/riscv/exact-branch-local.s: Test conditional branches and unconditional jumps relative to a local symbol. * testsuite/gas/riscv/exact-branch-local-noexact.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-ok.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-fail.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-fail.l: Ditto. * testsuite/gas/riscv/exact-branch-extern.s: Test conditional branches and unconditional jumps relative to an external symbol. * testsuite/gas/riscv/exact-branch-extern-noexact.d: Ditto. * testsuite/gas/riscv/exact-branch-extern-exact.d: Ditto. * testsuite/gas/riscv/li32.s: Enable exact mode by external option. * testsuite/gas/riscv/li64.s: Likewise. * testsuite/gas/riscv/exact-li32.d: li32.d but enable exact mode to make sure that no automatic instruction compression occurs. * testsuite/gas/riscv/exact-li64.d: Likewise. * testsuite/gas/riscv/no-relax-branch-offset-fail.s: Use exact mode to test various configurations and instructions. * testsuite/gas/riscv/no-relax-branch-offset-fail.d: Ditto. * testsuite/gas/riscv/no-relax-branch-offset-fail.l: Ditto. include/ChangeLog: * opcode/riscv.h (INSN_NON_EXACT): New flag to represent aliases to reject on the exact mode. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add INSN_NON_EXACT flag to all instructions that should be rejected on the exact mode.
1 parent 378d39e commit 6424ada

20 files changed

+784
-104
lines changed

‎gas/config/tc-riscv.c

Lines changed: 31 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -269,6 +269,7 @@ struct riscv_set_options
269269
int pic; /* Generate position-independent code. */
270270
int rvc; /* Generate RVC code. */
271271
int relax; /* Emit relocs the linker is allowed to relax. */
272+
int exact; /* Emit instructions without compression or relaxation. */
272273
int arch_attr; /* Emit architecture and privileged elf attributes. */
273274
int csr_check; /* Enable the CSR checking. */
274275
};
@@ -278,6 +279,7 @@ static struct riscv_set_options riscv_opts =
278279
0, /* pic */
279280
0, /* rvc */
280281
1, /* relax */
282+
0, /* exact */
281283
DEFAULT_RISCV_ATTR, /* arch_attr */
282284
0, /* csr_check */
283285
};
@@ -470,16 +472,18 @@ static bool explicit_priv_attr = false;
470472
static char *expr_parse_end;
471473

472474
/* Macros for encoding relaxation state for RVC branches and far jumps. */
473-
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
475+
#define RELAX_BRANCH_ENCODE(uncond, rvc, length, exact) \
474476
((relax_substateT) \
475477
(0xc0000000 \
476478
| ((uncond) ? 1 : 0) \
477479
| ((rvc) ? 2 : 0) \
478-
| ((length) << 2)))
480+
| ((length) << 2) \
481+
| ((exact) << 6)))
479482
#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
480483
#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
481484
#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
482485
#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
486+
#define RELAX_BRANCH_EXACT(i) (((i) & 0x40) != 0)
483487

484488
/* Is the given value a sign-extended 32-bit value? */
485489
#define IS_SEXT_32BIT_NUM(x) \
@@ -809,22 +813,25 @@ add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
809813
static unsigned
810814
relaxed_branch_length (fragS *fragp, asection *sec, int update)
811815
{
812-
int jump, rvc, length = 8;
816+
int jump, rvc, exact, length = 8;
813817

814818
if (!fragp)
815819
return length;
816820

817821
jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
818822
rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
823+
exact = RELAX_BRANCH_EXACT (fragp->fr_subtype);
819824
length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
820825

821826
/* Assume jumps are in range; the linker will catch any that aren't. */
822827
length = jump ? 4 : 8;
823828

824-
if (fragp->fr_symbol != NULL
825-
&& S_IS_DEFINED (fragp->fr_symbol)
826-
&& !S_IS_WEAK (fragp->fr_symbol)
827-
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
829+
if (exact)
830+
length = rvc ? 2 : 4;
831+
else if (fragp->fr_symbol != NULL
832+
&& S_IS_DEFINED (fragp->fr_symbol)
833+
&& !S_IS_WEAK (fragp->fr_symbol)
834+
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
828835
{
829836
offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
830837
bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
@@ -839,7 +846,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
839846
}
840847

841848
if (update)
842-
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
849+
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length, exact);
843850

844851
return length;
845852
}
@@ -1994,7 +2001,8 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
19942001
}
19952002

19962003
add_relaxed_insn (ip, worst_case, best_case,
1997-
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
2004+
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case,
2005+
riscv_opts.exact),
19982006
address_expr->X_add_symbol,
19992007
address_expr->X_add_number);
20002008
return;
@@ -2874,6 +2882,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
28742882
if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
28752883
continue;
28762884

2885+
if (insn->pinfo != INSN_MACRO && riscv_opts.exact
2886+
&& (insn->pinfo & INSN_NON_EXACT))
2887+
continue;
2888+
28772889
if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class))
28782890
{
28792891
error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
@@ -5088,6 +5100,16 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
50885100
riscv_opts.relax = true;
50895101
else if (strcmp (name, "norelax") == 0)
50905102
riscv_opts.relax = false;
5103+
else if (strcmp (name, "exact") == 0)
5104+
{
5105+
riscv_opts.exact = true;
5106+
riscv_opts.relax = false;
5107+
}
5108+
else if (strcmp (name, "noexact") == 0)
5109+
{
5110+
riscv_opts.exact = false;
5111+
riscv_opts.relax = true;
5112+
}
50915113
else if (strcmp (name, "csr-check") == 0)
50925114
riscv_opts.csr_check = true;
50935115
else if (strcmp (name, "no-csr-check") == 0)

‎gas/doc/c-riscv.texi

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,19 @@ Enables or disables relaxation. The RISC-V assembler and linker
212212
opportunistically relax some code sequences, but sometimes this behavior is not
213213
desirable.
214214

215+
@item exact
216+
@itemx noexact
217+
Enables or disables exact mode. Not only the exact mode disables linker
218+
relaxations, it also disables automatic instruction compression and the branch
219+
relaxation (both optionally change instruction encodings and/or instruction
220+
count). This mode is useful in some cases where the instruction sequences, as
221+
exactly written, are expected to be emitted.
222+
223+
Note that, in the current implementation, @samp{.option exact} implies
224+
@samp{.option norelax} and @samp{.option noexact} implies @samp{.option relax}.
225+
Due to their flaky interactions, it is strongly discouraged to use both
226+
@samp{.option relax/norelax} and @samp{.option exact/noexact} in the same scope.
227+
215228
@item csr-check
216229
@itemx no-csr-check
217230
Enables or disables the CSR checking.

‎gas/testsuite/gas/riscv/exact-branch-extern-exact.d

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
#as: -march=rv32ic --defsym exact_mode=1
2+
#source: exact-branch-extern.s
3+
#objdump: -drw -Mno-aliases
4+
5+
.*: file format .*
6+
7+
8+
Disassembly of section \.text:
9+
10+
0+ <\.text>:
11+
[ ]+[0-9a-f]+:[ ]+00b50063[ ]+beq[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
12+
[ ]+[0-9a-f]+:[ ]+feb51ee3[ ]+bne[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
13+
[ ]+[0-9a-f]+:[ ]+feb54ce3[ ]+blt[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
14+
[ ]+[0-9a-f]+:[ ]+feb55ae3[ ]+bge[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
15+
[ ]+[0-9a-f]+:[ ]+feb568e3[ ]+bltu[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
16+
[ ]+[0-9a-f]+:[ ]+feb576e3[ ]+bgeu[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
17+
[ ]+[0-9a-f]+:[ ]+d565[ ]+c\.beqz[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_BRANCH[ ]+ext
18+
[ ]+[0-9a-f]+:[ ]+f17d[ ]+c\.bnez[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_BRANCH[ ]+ext
19+
[ ]+[0-9a-f]+:[ ]+fea5c2e3[ ]+blt[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
20+
[ ]+[0-9a-f]+:[ ]+fea5d0e3[ ]+bge[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
21+
[ ]+[0-9a-f]+:[ ]+fca5eee3[ ]+bltu[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
22+
[ ]+[0-9a-f]+:[ ]+fca5fce3[ ]+bgeu[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
23+
[ ]+[0-9a-f]+:[ ]+fc050ae3[ ]+beq[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
24+
[ ]+[0-9a-f]+:[ ]+fc0518e3[ ]+bne[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
25+
[ ]+[0-9a-f]+:[ ]+fc0546e3[ ]+blt[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
26+
[ ]+[0-9a-f]+:[ ]+fca044e3[ ]+blt[ ]+zero,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
27+
[ ]+[0-9a-f]+:[ ]+fca052e3[ ]+bge[ ]+zero,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
28+
[ ]+[0-9a-f]+:[ ]+fc0550e3[ ]+bge[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
29+
[ ]+[0-9a-f]+:[ ]+0001[ ]+.*
30+
[ ]+[0-9a-f]+:[ ]+fbbff56f[ ]+jal[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
31+
[ ]+[0-9a-f]+:[ ]+bf5d[ ]+c\.j[ ]+[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_JUMP[ ]+ext
32+
[ ]+[0-9a-f]+:[ ]+3f55[ ]+c\.jal[ ]+[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_JUMP[ ]+ext

‎gas/testsuite/gas/riscv/exact-branch-extern-noexact.d

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
#as: -march=rv32ic
2+
#source: exact-branch-extern.s
3+
#objdump: -drw -Mno-aliases
4+
5+
.*: file format .*
6+
7+
8+
Disassembly of section \.text:
9+
10+
0+ <\.text>:
11+
[ ]+[0-9a-f]+:[ ]+00b51463[ ]+bne[ ]+a0,a1,[0-9a-f]+.*
12+
[ ]+[0-9a-f]+:[ ]+ffdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
13+
[ ]+[0-9a-f]+:[ ]+00b50463[ ]+beq[ ]+a0,a1,[0-9a-f]+.*
14+
[ ]+[0-9a-f]+:[ ]+ff5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
15+
[ ]+[0-9a-f]+:[ ]+00b55463[ ]+bge[ ]+a0,a1,[0-9a-f]+.*
16+
[ ]+[0-9a-f]+:[ ]+fedff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
17+
[ ]+[0-9a-f]+:[ ]+00b54463[ ]+blt[ ]+a0,a1,[0-9a-f]+.*
18+
[ ]+[0-9a-f]+:[ ]+fe5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
19+
[ ]+[0-9a-f]+:[ ]+00b57463[ ]+bgeu[ ]+a0,a1,[0-9a-f]+.*
20+
[ ]+[0-9a-f]+:[ ]+fddff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
21+
[ ]+[0-9a-f]+:[ ]+00b56463[ ]+bltu[ ]+a0,a1,[0-9a-f]+.*
22+
[ ]+[0-9a-f]+:[ ]+fd5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
23+
[ ]+[0-9a-f]+:[ ]+00051463[ ]+bne[ ]+a0,zero,[0-9a-f]+.*
24+
[ ]+[0-9a-f]+:[ ]+fcdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
25+
[ ]+[0-9a-f]+:[ ]+00050463[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
26+
[ ]+[0-9a-f]+:[ ]+fc5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
27+
[ ]+[0-9a-f]+:[ ]+00a5d463[ ]+bge[ ]+a1,a0,[0-9a-f]+.*
28+
[ ]+[0-9a-f]+:[ ]+fbdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
29+
[ ]+[0-9a-f]+:[ ]+00a5c463[ ]+blt[ ]+a1,a0,[0-9a-f]+.*
30+
[ ]+[0-9a-f]+:[ ]+fb5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
31+
[ ]+[0-9a-f]+:[ ]+00a5f463[ ]+bgeu[ ]+a1,a0,[0-9a-f]+.*
32+
[ ]+[0-9a-f]+:[ ]+fadff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
33+
[ ]+[0-9a-f]+:[ ]+00a5e463[ ]+bltu[ ]+a1,a0,[0-9a-f]+.*
34+
[ ]+[0-9a-f]+:[ ]+fa5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
35+
[ ]+[0-9a-f]+:[ ]+00051463[ ]+bne[ ]+a0,zero,[0-9a-f]+.*
36+
[ ]+[0-9a-f]+:[ ]+f9dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
37+
[ ]+[0-9a-f]+:[ ]+00050463[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
38+
[ ]+[0-9a-f]+:[ ]+f95ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
39+
[ ]+[0-9a-f]+:[ ]+00055463[ ]+bge[ ]+a0,zero,[0-9a-f]+.*
40+
[ ]+[0-9a-f]+:[ ]+f8dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
41+
[ ]+[0-9a-f]+:[ ]+00a05463[ ]+bge[ ]+zero,a0,[0-9a-f]+.*
42+
[ ]+[0-9a-f]+:[ ]+f85ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
43+
[ ]+[0-9a-f]+:[ ]+00a04463[ ]+blt[ ]+zero,a0,[0-9a-f]+.*
44+
[ ]+[0-9a-f]+:[ ]+f7dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
45+
[ ]+[0-9a-f]+:[ ]+00054463[ ]+blt[ ]+a0,zero,[0-9a-f]+.*
46+
[ ]+[0-9a-f]+:[ ]+f75ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
47+
[ ]+[0-9a-f]+:[ ]+0001[ ]+.*
48+
[ ]+[0-9a-f]+:[ ]+f6fff56f[ ]+jal[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
49+
[ ]+[0-9a-f]+:[ ]+f6bff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
50+
[ ]+[0-9a-f]+:[ ]+f67ff0ef[ ]+jal[ ]+ra,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext

‎gas/testsuite/gas/riscv/exact-branch-extern.s

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@@ -0,0 +1,40 @@
1+
.ifdef exact_mode
2+
.option exact
3+
.else
4+
.option noexact
5+
.endif
6+
.extern ext
7+
8+
## Conditional Branches
9+
10+
# Basic instructions
11+
beq a0, a1, ext
12+
bne a0, a1, ext
13+
blt a0, a1, ext
14+
bge a0, a1, ext
15+
bltu a0, a1, ext
16+
bgeu a0, a1, ext
17+
18+
# Compressed instructions
19+
c.beqz a0, ext
20+
c.bnez a0, ext
21+
22+
# Aliases
23+
bgt a0, a1, ext
24+
ble a0, a1, ext
25+
bgtu a0, a1, ext
26+
bleu a0, a1, ext
27+
beqz a0, ext
28+
bnez a0, ext
29+
bltz a0, ext
30+
bgtz a0, ext
31+
blez a0, ext
32+
bgez a0, ext
33+
34+
c.nop
35+
36+
## Unconditional Jumps (normal and compressed)
37+
38+
jal a0, ext
39+
c.j ext
40+
c.jal ext # RV32C only

‎gas/testsuite/gas/riscv/exact-branch-local-exact-fail.d

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#as: -march=rv32ic --defsym exact_mode=1 --defsym long_branch=1
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#source: exact-branch-local.s
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#error_output: exact-branch-local-exact-fail.l

‎gas/testsuite/gas/riscv/exact-branch-local-exact-fail.l

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.*Assembler messages:
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.*:93: Error: invalid B-type offset \(\+4096\)
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.*:94: Error: invalid B-type offset \(-4098\)
4+
.*:95: Error: invalid B-type offset \(\+4096\)
5+
.*:96: Error: invalid B-type offset \(-4098\)
6+
.*:97: Error: invalid B-type offset \(\+4096\)
7+
.*:98: Error: invalid B-type offset \(-4098\)
8+
.*:99: Error: invalid B-type offset \(\+4096\)
9+
.*:100: Error: invalid B-type offset \(-4098\)
10+
.*:101: Error: invalid B-type offset \(\+4096\)
11+
.*:102: Error: invalid B-type offset \(-4098\)
12+
.*:103: Error: invalid B-type offset \(\+4096\)
13+
.*:104: Error: invalid B-type offset \(-4098\)
14+
.*:105: Error: invalid B-type offset \(\+4096\)
15+
.*:106: Error: invalid B-type offset \(-4098\)
16+
.*:107: Error: invalid B-type offset \(\+4096\)
17+
.*:108: Error: invalid B-type offset \(-4098\)
18+
.*:109: Error: invalid B-type offset \(\+4096\)
19+
.*:110: Error: invalid B-type offset \(-4098\)
20+
.*:111: Error: invalid B-type offset \(\+4096\)
21+
.*:112: Error: invalid B-type offset \(-4098\)
22+
.*:113: Error: invalid B-type offset \(\+4096\)
23+
.*:114: Error: invalid B-type offset \(-4098\)
24+
.*:115: Error: invalid B-type offset \(\+4096\)
25+
.*:116: Error: invalid B-type offset \(-4098\)
26+
.*:117: Error: invalid B-type offset \(\+4096\)
27+
.*:118: Error: invalid B-type offset \(-4098\)
28+
.*:119: Error: invalid B-type offset \(\+4096\)
29+
.*:120: Error: invalid B-type offset \(-4098\)
30+
.*:121: Error: invalid B-type offset \(\+4096\)
31+
.*:122: Error: invalid B-type offset \(-4098\)
32+
.*:123: Error: invalid B-type offset \(\+4096\)
33+
.*:124: Error: invalid B-type offset \(-4098\)
34+
.*:128: Error: invalid CB-type offset \(\+256\)
35+
.*:129: Error: invalid CB-type offset \(-258\)
36+
.*:130: Error: invalid CB-type offset \(\+256\)
37+
.*:131: Error: invalid CB-type offset \(-258\)
38+
.*:132: Error: invalid J-type offset \(\+1048576\)
39+
.*:133: Error: invalid J-type offset \(-1048578\)
40+
.*:134: Error: invalid CJ-type offset \(\+2048\)
41+
.*:135: Error: invalid CJ-type offset \(-2050\)
42+
.*:136: Error: invalid CJ-type offset \(\+2048\)
43+
.*:137: Error: invalid CJ-type offset \(-2050\)

‎gas/testsuite/gas/riscv/exact-branch-local-exact-ok.d

Lines changed: 75 additions & 0 deletions
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#as: -march=rv32ic --defsym exact_mode=1
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#source: exact-branch-local.s
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#objdump: -d -Mno-aliases
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.*: file format .*
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Disassembly of section \.text:
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0+ <\.text>:
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[ ]+[0-9a-f]+:[ ]+80050063[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+80b51063[ ]+bne[ ]+a0,a1,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+7eb55fe3[ ]+bge[ ]+a0,a1,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+7eb57fe3[ ]+bgeu[ ]+a0,a1,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+7ea5cfe3[ ]+blt[ ]+a1,a0,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+7ea5efe3[ ]+bltu[ ]+a1,a0,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+7ea5ffe3[ ]+bgeu[ ]+a1,a0,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+80050063[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
57+
[ ]+[0-9a-f]+:[ ]+7e051fe3[ ]+bne[ ]+a0,zero,[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+a001[ ]+c\.j[ ]+[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+2001[ ]+c\.jal[ ]+[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+affd[ ]+c\.j[ ]+[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+2ffd[ ]+c\.jal[ ]+[0-9a-f]+.*
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[ ]+[0-9a-f]+:[ ]+3001[ ]+c\.jal[ ]+[0-9a-f]+.*

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