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RISC-V: Support ".option [no]exact" assembler directives
This commit adds two assembler directives: ".option exact" and ".option noexact" (enable/disable the exact mode) as discussed in <riscv-non-isa/riscv-asm-manual#122>. When the exact mode is enabled, 1. Linker relaxations are turned off, 2. Instruction aliases that will change the encoding from the (likely non-alias) instruction with the same name are disabled (e.g. "addi" will never turn into "c.addi" even if optimizable) and 3. Assembler relaxation of branch instructions are disabled (e.g. "blt" with a long offset will not turn into "bge + j"). The main purpose of this mode is to emit desired machine code as the user writes, assuming the user knows constraints of their code. So, macros like "li" (known to be expanded into possibly complex sequences) without single instruction encoding are not fully aware of this mode. Currently, interactions between ".option relax/norelax" and ".option exact/noexact" are designed to be LLVM-compatible (i.e. ".option exact/noexact" imply ".option norelax/relax", respectively). cf. <llvm/llvm-project#122483> gas/ChangeLog: * config/tc-riscv.c (struct riscv_set_options): Add exact option. (RELAX_BRANCH_ENCODE): Encode exact option. (RELAX_BRANCH_EXACT): New predicate macro. (relaxed_branch_length): Handle exact mode cases. (append_insn): Pass exact option to RELAX_BRANCH_ENCODE. (riscv_ip): Skip instructions that would change the encoding when the exact mode is enabled. (s_riscv_option): Parse ".option exact" and ".option noexact" assembler directives. * doc/c-riscv.texi: Document new assembler directives. * testsuite/gas/riscv/exact.s: Test exact mode basics. * testsuite/gas/riscv/exact.d: Ditto. * testsuite/gas/riscv/exact-branch-local.s: Test conditional branches and unconditional jumps relative to a local symbol. * testsuite/gas/riscv/exact-branch-local-noexact.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-ok.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-fail.d: Ditto. * testsuite/gas/riscv/exact-branch-local-exact-fail.l: Ditto. * testsuite/gas/riscv/exact-branch-extern.s: Test conditional branches and unconditional jumps relative to an external symbol. * testsuite/gas/riscv/exact-branch-extern-noexact.d: Ditto. * testsuite/gas/riscv/exact-branch-extern-exact.d: Ditto. * testsuite/gas/riscv/no-relax-branch-offset-fail.s: Use exact mode to test various configurations and instructions. * testsuite/gas/riscv/no-relax-branch-offset-fail.d: Ditto. * testsuite/gas/riscv/no-relax-branch-offset-fail.l: Ditto. include/ChangeLog: * opcode/riscv.h (INSN_NON_EXACT): New flag to represent aliases to reject on the exact mode. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add INSN_NON_EXACT flag to all instructions that should be rejected on the exact mode.
1 parent e28a8ff commit a19f2bc

16 files changed

+698
-99
lines changed

‎gas/config/tc-riscv.c

Lines changed: 30 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,7 @@ struct riscv_set_options
268268
int pic; /* Generate position-independent code. */
269269
int rvc; /* Generate RVC code. */
270270
int relax; /* Emit relocs the linker is allowed to relax. */
271+
int exact; /* Emit instructions without compression or relaxation. */
271272
int arch_attr; /* Emit architecture and privileged elf attributes. */
272273
int csr_check; /* Enable the CSR checking. */
273274
};
@@ -277,6 +278,7 @@ static struct riscv_set_options riscv_opts =
277278
0, /* pic */
278279
0, /* rvc */
279280
1, /* relax */
281+
0, /* exact */
280282
DEFAULT_RISCV_ATTR, /* arch_attr */
281283
0, /* csr_check */
282284
};
@@ -469,16 +471,18 @@ static bool explicit_priv_attr = false;
469471
static char *expr_parse_end;
470472

471473
/* Macros for encoding relaxation state for RVC branches and far jumps. */
472-
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
474+
#define RELAX_BRANCH_ENCODE(uncond, rvc, length, exact) \
473475
((relax_substateT) \
474476
(0xc0000000 \
475477
| ((uncond) ? 1 : 0) \
476478
| ((rvc) ? 2 : 0) \
477-
| ((length) << 2)))
479+
| ((length) << 2) \
480+
| ((exact) << 6)))
478481
#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
479482
#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
480483
#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
481484
#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
485+
#define RELAX_BRANCH_EXACT(i) (((i) & 0x40) != 0)
482486

483487
/* Is the given value a sign-extended 32-bit value? */
484488
#define IS_SEXT_32BIT_NUM(x) \
@@ -808,22 +812,25 @@ add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
808812
static unsigned
809813
relaxed_branch_length (fragS *fragp, asection *sec, int update)
810814
{
811-
int jump, rvc, length = 8;
815+
int jump, rvc, exact, length = 8;
812816

813817
if (!fragp)
814818
return length;
815819

816820
jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
817821
rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
822+
exact = RELAX_BRANCH_EXACT (fragp->fr_subtype);
818823
length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
819824

820825
/* Assume jumps are in range; the linker will catch any that aren't. */
821826
length = jump ? 4 : 8;
822827

823-
if (fragp->fr_symbol != NULL
824-
&& S_IS_DEFINED (fragp->fr_symbol)
825-
&& !S_IS_WEAK (fragp->fr_symbol)
826-
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
828+
if (exact)
829+
length = rvc ? 2 : 4;
830+
else if (fragp->fr_symbol != NULL
831+
&& S_IS_DEFINED (fragp->fr_symbol)
832+
&& !S_IS_WEAK (fragp->fr_symbol)
833+
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
827834
{
828835
offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
829836
bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
@@ -838,7 +845,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
838845
}
839846

840847
if (update)
841-
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
848+
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length, exact);
842849

843850
return length;
844851
}
@@ -1990,7 +1997,8 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
19901997
}
19911998

19921999
add_relaxed_insn (ip, worst_case, best_case,
1993-
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
2000+
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case,
2001+
riscv_opts.exact),
19942002
address_expr->X_add_symbol,
19952003
address_expr->X_add_number);
19962004
return;
@@ -2870,6 +2878,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
28702878
if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
28712879
continue;
28722880

2881+
if (riscv_opts.exact && (insn->pinfo & INSN_NON_EXACT))
2882+
continue;
2883+
28732884
if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class))
28742885
{
28752886
error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
@@ -5089,6 +5100,16 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
50895100
riscv_opts.relax = true;
50905101
else if (strcmp (name, "norelax") == 0)
50915102
riscv_opts.relax = false;
5103+
else if (strcmp (name, "exact") == 0)
5104+
{
5105+
riscv_opts.exact = true;
5106+
riscv_opts.relax = false;
5107+
}
5108+
else if (strcmp (name, "noexact") == 0)
5109+
{
5110+
riscv_opts.exact = false;
5111+
riscv_opts.relax = true;
5112+
}
50925113
else if (strcmp (name, "csr-check") == 0)
50935114
riscv_opts.csr_check = true;
50945115
else if (strcmp (name, "no-csr-check") == 0)

‎gas/doc/c-riscv.texi

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,17 @@ Enables or disables relaxation. The RISC-V assembler and linker
210210
opportunistically relax some code sequences, but sometimes this behavior is not
211211
desirable.
212212

213+
@item exact
214+
@itemx noexact
215+
Enables or disables exact mode. Not only the exact mode disables linker
216+
relaxations, it also disables automatic instruction compression and the branch
217+
relaxation (both optionally change instruction encodings and/or instruction
218+
count). This mode is useful in some cases where the instruction sequences, as
219+
exactly written, are expected to be emitted.
220+
221+
Note that, @samp{.option exact} implies @samp{.option norelax} and
222+
@samp{.option noexact} implies @samp{.option relax}.
223+
213224
@item csr-check
214225
@itemx no-csr-check
215226
Enables or disables the CSR checking.

‎gas/testsuite/gas/riscv/exact-branch-extern-exact.d

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
#as: -march=rv32ic --defsym exact_mode=1
2+
#source: exact-branch-extern.s
3+
#objdump: -drw -Mno-aliases
4+
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.*: file format .*
6+
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Disassembly of section \.text:
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0+ <\.text>:
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[ ]+[0-9a-f]+:[ ]+00b50063[ ]+beq[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
12+
[ ]+[0-9a-f]+:[ ]+feb51ee3[ ]+bne[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
13+
[ ]+[0-9a-f]+:[ ]+feb54ce3[ ]+blt[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
14+
[ ]+[0-9a-f]+:[ ]+feb55ae3[ ]+bge[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
15+
[ ]+[0-9a-f]+:[ ]+feb568e3[ ]+bltu[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
16+
[ ]+[0-9a-f]+:[ ]+feb576e3[ ]+bgeu[ ]+a0,a1,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
17+
[ ]+[0-9a-f]+:[ ]+d565[ ]+c\.beqz[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_BRANCH[ ]+ext
18+
[ ]+[0-9a-f]+:[ ]+f17d[ ]+c\.bnez[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_BRANCH[ ]+ext
19+
[ ]+[0-9a-f]+:[ ]+fea5c2e3[ ]+blt[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
20+
[ ]+[0-9a-f]+:[ ]+fea5d0e3[ ]+bge[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
21+
[ ]+[0-9a-f]+:[ ]+fca5eee3[ ]+bltu[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
22+
[ ]+[0-9a-f]+:[ ]+fca5fce3[ ]+bgeu[ ]+a1,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
23+
[ ]+[0-9a-f]+:[ ]+fc050ae3[ ]+beq[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
24+
[ ]+[0-9a-f]+:[ ]+fc0518e3[ ]+bne[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
25+
[ ]+[0-9a-f]+:[ ]+fc0546e3[ ]+blt[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
26+
[ ]+[0-9a-f]+:[ ]+fca044e3[ ]+blt[ ]+zero,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
27+
[ ]+[0-9a-f]+:[ ]+fca052e3[ ]+bge[ ]+zero,a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
28+
[ ]+[0-9a-f]+:[ ]+fc0550e3[ ]+bge[ ]+a0,zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_BRANCH[ ]+ext
29+
[ ]+[0-9a-f]+:[ ]+0001[ ]+.*
30+
[ ]+[0-9a-f]+:[ ]+fbbff56f[ ]+jal[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
31+
[ ]+[0-9a-f]+:[ ]+bf5d[ ]+c\.j[ ]+[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_JUMP[ ]+ext
32+
[ ]+[0-9a-f]+:[ ]+3f55[ ]+c\.jal[ ]+[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_RVC_JUMP[ ]+ext

‎gas/testsuite/gas/riscv/exact-branch-extern-noexact.d

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
#as: -march=rv32ic
2+
#source: exact-branch-extern.s
3+
#objdump: -drw -Mno-aliases
4+
5+
.*: file format .*
6+
7+
8+
Disassembly of section \.text:
9+
10+
0+ <\.text>:
11+
[ ]+[0-9a-f]+:[ ]+00b51463[ ]+bne[ ]+a0,a1,[0-9a-f]+.*
12+
[ ]+[0-9a-f]+:[ ]+ffdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
13+
[ ]+[0-9a-f]+:[ ]+00b50463[ ]+beq[ ]+a0,a1,[0-9a-f]+.*
14+
[ ]+[0-9a-f]+:[ ]+ff5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
15+
[ ]+[0-9a-f]+:[ ]+00b55463[ ]+bge[ ]+a0,a1,[0-9a-f]+.*
16+
[ ]+[0-9a-f]+:[ ]+fedff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
17+
[ ]+[0-9a-f]+:[ ]+00b54463[ ]+blt[ ]+a0,a1,[0-9a-f]+.*
18+
[ ]+[0-9a-f]+:[ ]+fe5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
19+
[ ]+[0-9a-f]+:[ ]+00b57463[ ]+bgeu[ ]+a0,a1,[0-9a-f]+.*
20+
[ ]+[0-9a-f]+:[ ]+fddff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
21+
[ ]+[0-9a-f]+:[ ]+00b56463[ ]+bltu[ ]+a0,a1,[0-9a-f]+.*
22+
[ ]+[0-9a-f]+:[ ]+fd5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
23+
[ ]+[0-9a-f]+:[ ]+00051463[ ]+bne[ ]+a0,zero,[0-9a-f]+.*
24+
[ ]+[0-9a-f]+:[ ]+fcdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
25+
[ ]+[0-9a-f]+:[ ]+00050463[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
26+
[ ]+[0-9a-f]+:[ ]+fc5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
27+
[ ]+[0-9a-f]+:[ ]+00a5d463[ ]+bge[ ]+a1,a0,[0-9a-f]+.*
28+
[ ]+[0-9a-f]+:[ ]+fbdff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
29+
[ ]+[0-9a-f]+:[ ]+00a5c463[ ]+blt[ ]+a1,a0,[0-9a-f]+.*
30+
[ ]+[0-9a-f]+:[ ]+fb5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
31+
[ ]+[0-9a-f]+:[ ]+00a5f463[ ]+bgeu[ ]+a1,a0,[0-9a-f]+.*
32+
[ ]+[0-9a-f]+:[ ]+fadff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
33+
[ ]+[0-9a-f]+:[ ]+00a5e463[ ]+bltu[ ]+a1,a0,[0-9a-f]+.*
34+
[ ]+[0-9a-f]+:[ ]+fa5ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
35+
[ ]+[0-9a-f]+:[ ]+00051463[ ]+bne[ ]+a0,zero,[0-9a-f]+.*
36+
[ ]+[0-9a-f]+:[ ]+f9dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
37+
[ ]+[0-9a-f]+:[ ]+00050463[ ]+beq[ ]+a0,zero,[0-9a-f]+.*
38+
[ ]+[0-9a-f]+:[ ]+f95ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
39+
[ ]+[0-9a-f]+:[ ]+00055463[ ]+bge[ ]+a0,zero,[0-9a-f]+.*
40+
[ ]+[0-9a-f]+:[ ]+f8dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
41+
[ ]+[0-9a-f]+:[ ]+00a05463[ ]+bge[ ]+zero,a0,[0-9a-f]+.*
42+
[ ]+[0-9a-f]+:[ ]+f85ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
43+
[ ]+[0-9a-f]+:[ ]+00a04463[ ]+blt[ ]+zero,a0,[0-9a-f]+.*
44+
[ ]+[0-9a-f]+:[ ]+f7dff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
45+
[ ]+[0-9a-f]+:[ ]+00054463[ ]+blt[ ]+a0,zero,[0-9a-f]+.*
46+
[ ]+[0-9a-f]+:[ ]+f75ff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
47+
[ ]+[0-9a-f]+:[ ]+0001[ ]+.*
48+
[ ]+[0-9a-f]+:[ ]+f6fff56f[ ]+jal[ ]+a0,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
49+
[ ]+[0-9a-f]+:[ ]+f6bff06f[ ]+jal[ ]+zero,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext
50+
[ ]+[0-9a-f]+:[ ]+f67ff0ef[ ]+jal[ ]+ra,[0-9a-f]+.*[0-9a-f]+:[ ]+R_RISCV_JAL[ ]+ext

‎gas/testsuite/gas/riscv/exact-branch-extern.s

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
.ifdef exact_mode
2+
.option exact
3+
.else
4+
.option noexact
5+
.endif
6+
.extern ext
7+
8+
## Conditional Branches
9+
10+
# Basic instructions
11+
beq a0, a1, ext
12+
bne a0, a1, ext
13+
blt a0, a1, ext
14+
bge a0, a1, ext
15+
bltu a0, a1, ext
16+
bgeu a0, a1, ext
17+
18+
# Compressed instructions
19+
c.beqz a0, ext
20+
c.bnez a0, ext
21+
22+
# Aliases
23+
bgt a0, a1, ext
24+
ble a0, a1, ext
25+
bgtu a0, a1, ext
26+
bleu a0, a1, ext
27+
beqz a0, ext
28+
bnez a0, ext
29+
bltz a0, ext
30+
bgtz a0, ext
31+
blez a0, ext
32+
bgez a0, ext
33+
34+
c.nop
35+
36+
## Unconditional Jumps (normal and compressed)
37+
38+
jal a0, ext
39+
c.j ext
40+
c.jal ext # RV32C only

‎gas/testsuite/gas/riscv/exact-branch-local-exact-fail.d

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@@ -0,0 +1,3 @@
1+
#as: -march=rv32ic --defsym exact_mode=1 --defsym long_branch=1
2+
#source: exact-branch-local.s
3+
#error_output: exact-branch-local-exact-fail.l

‎gas/testsuite/gas/riscv/exact-branch-local-exact-fail.l

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1+
.*Assembler messages:
2+
.*:93: Error: offset \(\+4096\) is invalid for B-type immediate
3+
.*:94: Error: offset \(-4098\) is invalid for B-type immediate
4+
.*:95: Error: offset \(\+4096\) is invalid for B-type immediate
5+
.*:96: Error: offset \(-4098\) is invalid for B-type immediate
6+
.*:97: Error: offset \(\+4096\) is invalid for B-type immediate
7+
.*:98: Error: offset \(-4098\) is invalid for B-type immediate
8+
.*:99: Error: offset \(\+4096\) is invalid for B-type immediate
9+
.*:100: Error: offset \(-4098\) is invalid for B-type immediate
10+
.*:101: Error: offset \(\+4096\) is invalid for B-type immediate
11+
.*:102: Error: offset \(-4098\) is invalid for B-type immediate
12+
.*:103: Error: offset \(\+4096\) is invalid for B-type immediate
13+
.*:104: Error: offset \(-4098\) is invalid for B-type immediate
14+
.*:105: Error: offset \(\+4096\) is invalid for B-type immediate
15+
.*:106: Error: offset \(-4098\) is invalid for B-type immediate
16+
.*:107: Error: offset \(\+4096\) is invalid for B-type immediate
17+
.*:108: Error: offset \(-4098\) is invalid for B-type immediate
18+
.*:109: Error: offset \(\+4096\) is invalid for B-type immediate
19+
.*:110: Error: offset \(-4098\) is invalid for B-type immediate
20+
.*:111: Error: offset \(\+4096\) is invalid for B-type immediate
21+
.*:112: Error: offset \(-4098\) is invalid for B-type immediate
22+
.*:113: Error: offset \(\+4096\) is invalid for B-type immediate
23+
.*:114: Error: offset \(-4098\) is invalid for B-type immediate
24+
.*:115: Error: offset \(\+4096\) is invalid for B-type immediate
25+
.*:116: Error: offset \(-4098\) is invalid for B-type immediate
26+
.*:117: Error: offset \(\+4096\) is invalid for B-type immediate
27+
.*:118: Error: offset \(-4098\) is invalid for B-type immediate
28+
.*:119: Error: offset \(\+4096\) is invalid for B-type immediate
29+
.*:120: Error: offset \(-4098\) is invalid for B-type immediate
30+
.*:121: Error: offset \(\+4096\) is invalid for B-type immediate
31+
.*:122: Error: offset \(-4098\) is invalid for B-type immediate
32+
.*:123: Error: offset \(\+4096\) is invalid for B-type immediate
33+
.*:124: Error: offset \(-4098\) is invalid for B-type immediate
34+
.*:128: Error: offset \(\+256\) is invalid for CB-type immediate
35+
.*:129: Error: offset \(-258\) is invalid for CB-type immediate
36+
.*:130: Error: offset \(\+256\) is invalid for CB-type immediate
37+
.*:131: Error: offset \(-258\) is invalid for CB-type immediate
38+
.*:132: Error: offset \(\+1048576\) is invalid for J-type immediate
39+
.*:133: Error: offset \(-1048578\) is invalid for J-type immediate
40+
.*:134: Error: offset \(\+2048\) is invalid for CJ-type immediate
41+
.*:135: Error: offset \(-2050\) is invalid for CJ-type immediate
42+
.*:136: Error: offset \(\+2048\) is invalid for CJ-type immediate
43+
.*:137: Error: offset \(-2050\) is invalid for CJ-type immediate

‎gas/testsuite/gas/riscv/exact-branch-local-exact-ok.d

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#as: -march=rv32ic --defsym exact_mode=1
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#source: exact-branch-local.s
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#objdump: -d -Mno-aliases
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.*: file format .*
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Disassembly of section \.text:
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0+ <\.text>:
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57+
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