|
34 | 34 | import digitalio
|
35 | 35 | from micropython import const
|
36 | 36 |
|
37 |
| -#try: |
38 |
| -# from warnings import warn |
39 |
| -#except ImportError: |
40 |
| - |
41 |
| -# def warn(msg, **kwargs): |
42 |
| -# "Issue a warning to stdout." |
43 |
| -# print( |
44 |
| -# "%s: %s" |
45 |
| -# % ("Warning" if kwargs.get("cat") is None else kwargs["cat"].__name__, msg) |
46 |
| -# ) |
47 |
| - |
48 | 37 |
|
49 | 38 | import adafruit_bus_device.spi_device as spidev
|
50 | 39 |
|
|
58 | 47 | # Register names (FSK Mode even though we use LoRa instead, from table 85)
|
59 | 48 | _RH_RF95_REG_00_FIFO = const(0x00)
|
60 | 49 | _RH_RF95_REG_01_OP_MODE = const(0x01)
|
61 |
| -#_RH_RF95_REG_02_RESERVED = const(0x02) |
62 |
| -#_RH_RF95_REG_03_RESERVED = const(0x03) |
63 |
| -#_RH_RF95_REG_04_RESERVED = const(0x04) |
64 |
| -#_RH_RF95_REG_05_RESERVED = const(0x05) |
65 | 50 | _RH_RF95_REG_06_FRF_MSB = const(0x06)
|
66 | 51 | _RH_RF95_REG_07_FRF_MID = const(0x07)
|
67 | 52 | _RH_RF95_REG_08_FRF_LSB = const(0x08)
|
|
108 | 93 | _RH_RF95_REG_63_AGC_THRESH2 = const(0x63)
|
109 | 94 | _RH_RF95_REG_64_AGC_THRESH3 = const(0x64)
|
110 | 95 |
|
111 |
| -# RH_RF95_REG_01_OP_MODE 0x01 |
112 |
| -#_RH_RF95_LONG_RANGE_MODE = const(0x80) |
113 |
| -#_RH_RF95_ACCESS_SHARED_REG = const(0x40) |
114 |
| -#_RH_RF95_MODE = const(0x07) |
115 |
| -#_RH_RF95_MODE_SLEEP = const(0x00) |
116 |
| -#_RH_RF95_MODE_STDBY = const(0x01) |
117 |
| -#_RH_RF95_MODE_FSTX = const(0x02) |
118 |
| -#_RH_RF95_MODE_TX = const(0x03) |
119 |
| -#_RH_RF95_MODE_FSRX = const(0x04) |
120 |
| -#_RH_RF95_MODE_RXCONTINUOUS = const(0x05) |
121 |
| -#_RH_RF95_MODE_RXSINGLE = const(0x06) |
122 |
| -#_RH_RF95_MODE_CAD = const(0x07) |
123 |
| - |
124 |
| -# RH_RF95_REG_09_PA_CONFIG 0x09 |
125 |
| -#_RH_RF95_PA_SELECT = const(0x80) |
126 |
| -#_RH_RF95_MAX_POWER = const(0x70) |
127 |
| -#_RH_RF95_OUTPUT_POWER = const(0x0F) |
128 |
| - |
129 |
| -# RH_RF95_REG_0A_PA_RAMP 0x0a |
130 |
| -#_RH_RF95_LOW_PN_TX_PLL_OFF = const(0x10) |
131 |
| -#_RH_RF95_PA_RAMP = const(0x0F) |
132 |
| -#_RH_RF95_PA_RAMP_3_4MS = const(0x00) |
133 |
| -#_RH_RF95_PA_RAMP_2MS = const(0x01) |
134 |
| -#_RH_RF95_PA_RAMP_1MS = const(0x02) |
135 |
| -#_RH_RF95_PA_RAMP_500US = const(0x03) |
136 |
| -#_RH_RF95_PA_RAMP_250US = const(0x04) |
137 |
| -#_RH_RF95_PA_RAMP_125US = const(0x05) |
138 |
| -#_RH_RF95_PA_RAMP_100US = const(0x06) |
139 |
| -#_RH_RF95_PA_RAMP_62US = const(0x07) |
140 |
| -#_RH_RF95_PA_RAMP_50US = const(0x08) |
141 |
| -#_RH_RF95_PA_RAMP_40US = const(0x09) |
142 |
| -#_RH_RF95_PA_RAMP_31US = const(0x0A) |
143 |
| -#_RH_RF95_PA_RAMP_25US = const(0x0B) |
144 |
| -#_RH_RF95_PA_RAMP_20US = const(0x0C) |
145 |
| -#_RH_RF95_PA_RAMP_15US = const(0x0D) |
146 |
| -#_RH_RF95_PA_RAMP_12US = const(0x0E) |
147 |
| -#_RH_RF95_PA_RAMP_10US = const(0x0F) |
148 |
| - |
149 |
| -# RH_RF95_REG_0B_OCP 0x0b |
150 |
| -#_RH_RF95_OCP_ON = const(0x20) |
151 |
| -#_RH_RF95_OCP_TRIM = const(0x1F) |
152 |
| - |
153 |
| -# RH_RF95_REG_0C_LNA 0x0c |
154 |
| -#_RH_RF95_LNA_GAIN = const(0xE0) |
155 |
| -#_RH_RF95_LNA_BOOST = const(0x03) |
156 |
| -#_RH_RF95_LNA_BOOST_DEFAULT = const(0x00) |
157 |
| -#_RH_RF95_LNA_BOOST_150PC = const(0x11) |
158 |
| - |
159 |
| -# RH_RF95_REG_11_IRQ_FLAGS_MASK 0x11 |
160 |
| -#_RH_RF95_RX_TIMEOUT_MASK = const(0x80) |
161 |
| -#_RH_RF95_RX_DONE_MASK = const(0x40) |
162 |
| -#_RH_RF95_PAYLOAD_CRC_ERROR_MASK = const(0x20) |
163 |
| -#_RH_RF95_VALID_HEADER_MASK = const(0x10) |
164 |
| -#_RH_RF95_TX_DONE_MASK = const(0x08) |
165 |
| -#_RH_RF95_CAD_DONE_MASK = const(0x04) |
166 |
| -#_RH_RF95_FHSS_CHANGE_CHANNEL_MASK = const(0x02) |
167 |
| -#_RH_RF95_CAD_DETECTED_MASK = const(0x01) |
168 |
| - |
169 |
| -# RH_RF95_REG_12_IRQ_FLAGS 0x12 |
170 |
| -#_RH_RF95_RX_TIMEOUT = const(0x80) |
171 |
| -#_RH_RF95_RX_DONE = const(0x40) |
172 |
| -#_RH_RF95_PAYLOAD_CRC_ERROR = const(0x20) |
173 |
| -#_RH_RF95_VALID_HEADER = const(0x10) |
174 |
| -#_RH_RF95_TX_DONE = const(0x08) |
175 |
| -#_RH_RF95_CAD_DONE = const(0x04) |
176 |
| -#_RH_RF95_FHSS_CHANGE_CHANNEL = const(0x02) |
177 |
| -#_RH_RF95_CAD_DETECTED = const(0x01) |
178 |
| - |
179 |
| -# RH_RF95_REG_18_MODEM_STAT 0x18 |
180 |
| -#_RH_RF95_RX_CODING_RATE = const(0xE0) |
181 |
| -#_RH_RF95_MODEM_STATUS_CLEAR = const(0x10) |
182 |
| -#_RH_RF95_MODEM_STATUS_HEADER_INFO_VALID = const(0x08) |
183 |
| -#_RH_RF95_MODEM_STATUS_RX_ONGOING = const(0x04) |
184 |
| -#_RH_RF95_MODEM_STATUS_SIGNAL_SYNCHRONIZED = const(0x02) |
185 |
| -#_RH_RF95_MODEM_STATUS_SIGNAL_DETECTED = const(0x01) |
186 |
| - |
187 |
| -# RH_RF95_REG_1C_HOP_CHANNEL 0x1c |
188 |
| -#_RH_RF95_PLL_TIMEOUT = const(0x80) |
189 |
| -#_RH_RF95_RX_PAYLOAD_CRC_IS_ON = const(0x40) |
190 |
| -#_RH_RF95_FHSS_PRESENT_CHANNEL = const(0x3F) |
191 |
| - |
192 |
| -# RH_RF95_REG_1D_MODEM_CONFIG1 0x1d |
193 |
| -#_RH_RF95_BW = const(0xC0) |
194 |
| -#_RH_RF95_BW_125KHZ = const(0x00) |
195 |
| -#_RH_RF95_BW_250KHZ = const(0x40) |
196 |
| -#_RH_RF95_BW_500KHZ = const(0x80) |
197 |
| -#_RH_RF95_BW_RESERVED = const(0xC0) |
198 |
| -#_RH_RF95_CODING_RATE = const(0x38) |
199 |
| -#_RH_RF95_CODING_RATE_4_5 = const(0x00) |
200 |
| -#_RH_RF95_CODING_RATE_4_6 = const(0x08) |
201 |
| -#_RH_RF95_CODING_RATE_4_7 = const(0x10) |
202 |
| -#_RH_RF95_CODING_RATE_4_8 = const(0x18) |
203 |
| -#_RH_RF95_IMPLICIT_HEADER_MODE_ON = const(0x04) |
204 |
| -#_RH_RF95_RX_PAYLOAD_CRC_ON = const(0x02) |
205 |
| -#_RH_RF95_LOW_DATA_RATE_OPTIMIZE = const(0x01) |
206 |
| - |
207 |
| -# RH_RF95_REG_1E_MODEM_CONFIG2 0x1e |
208 | 96 | _RH_RF95_DETECTION_OPTIMIZE = const(0x31)
|
209 | 97 | _RH_RF95_DETECTION_THRESHOLD = const(0x37)
|
210 |
| -#_RH_RF95_SPREADING_FACTOR = const(0xF0) |
211 |
| -#_RH_RF95_SPREADING_FACTOR_64CPS = const(0x60) |
212 |
| -#_RH_RF95_SPREADING_FACTOR_128CPS = const(0x70) |
213 |
| -#_RH_RF95_SPREADING_FACTOR_256CPS = const(0x80) |
214 |
| -#_RH_RF95_SPREADING_FACTOR_512CPS = const(0x90) |
215 |
| -#_RH_RF95_SPREADING_FACTOR_1024CPS = const(0xA0) |
216 |
| -#_RH_RF95_SPREADING_FACTOR_2048CPS = const(0xB0) |
217 |
| -#_RH_RF95_SPREADING_FACTOR_4096CPS = const(0xC0) |
218 |
| -#_RH_RF95_TX_CONTINUOUS_MOE = const(0x08) |
219 |
| -#_RH_RF95_AGC_AUTO_ON = const(0x04) |
220 |
| -#_RH_RF95_SYM_TIMEOUT_MSB = const(0x03) |
221 |
| - |
222 |
| -# RH_RF95_REG_4D_PA_DAC 0x4d |
| 98 | + |
223 | 99 | _RH_RF95_PA_DAC_DISABLE = const(0x04)
|
224 | 100 | _RH_RF95_PA_DAC_ENABLE = const(0x07)
|
225 | 101 |
|
@@ -352,8 +228,6 @@ def __set__(self, obj, val):
|
352 | 228 |
|
353 | 229 | dio0_mapping = _RegisterBits(_RH_RF95_REG_40_DIO_MAPPING1, offset=6, bits=2)
|
354 | 230 |
|
355 |
| - crc_error = _RegisterBits(_RH_RF95_REG_12_IRQ_FLAGS, offset=5, bits=1) |
356 |
| - |
357 | 231 | bw_bins = (7800, 10400, 15600, 20800, 31250, 41700, 62500, 125000, 250000)
|
358 | 232 |
|
359 | 233 | def __init__(
|
@@ -722,6 +596,10 @@ def rx_done(self):
|
722 | 596 | """Receive status"""
|
723 | 597 | return (self._read_u8(_RH_RF95_REG_12_IRQ_FLAGS) & 0x40) >> 6
|
724 | 598 |
|
| 599 | + def crc_error(self): |
| 600 | + """crc status""" |
| 601 | + return (self._read_u8(_RH_RF95_REG_12_IRQ_FLAGS) & 0x20) >> 5 |
| 602 | + |
725 | 603 |
|
726 | 604 | def send(
|
727 | 605 | self,
|
@@ -876,9 +754,8 @@ def receive(
|
876 | 754 | # Enter idle mode to stop receiving other packets.
|
877 | 755 | self.idle()
|
878 | 756 | if not timed_out:
|
879 |
| - if self.enable_crc and self.crc_error: |
| 757 | + if self.enable_crc and self.crc_error(): |
880 | 758 | self.crc_error_count += 1
|
881 |
| -# warn("CRC error, packet ignored") |
882 | 759 | else:
|
883 | 760 | # Read the data from the FIFO.
|
884 | 761 | # Read the length of the FIFO.
|
@@ -911,10 +788,9 @@ def receive(
|
911 | 788 | # delay before sending Ack to give receiver a chance to get ready
|
912 | 789 | if self.ack_delay is not None:
|
913 | 790 | time.sleep(self.ack_delay)
|
914 |
| - # send ACK packet to sender |
915 |
| - data = bytes("!", "UTF-8") |
| 791 | + # send ACK packet to sender (data is b'!') |
916 | 792 | self.send(
|
917 |
| - data, |
| 793 | + b'!', |
918 | 794 | destination=packet[1],
|
919 | 795 | node=packet[0],
|
920 | 796 | identifier=packet[2],
|
|
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