@@ -176,6 +176,8 @@ enum {
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//--------------------------------------------------------------------+
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typedef struct {
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+ uint8_t daddr ;
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+
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struct TU_ATTR_PACKED {
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uint8_t ep_dir : 1 ;
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uint8_t is_iso : 1 ;
@@ -184,17 +186,19 @@ typedef struct {
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uint8_t xfer_pending : 1 ;
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uint8_t xfer_complete : 1 ;
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};
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+
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struct TU_ATTR_PACKED {
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- uint8_t daddr : 4 ;
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uint8_t ep_num : 4 ;
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+ uint16_t packet_size : 12 ;
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};
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- uint16_t packet_size ;
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uint16_t total_len ;
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uint16_t xferred_len ;
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uint8_t * buf ;
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} max3421_ep_t ;
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+ TU_VERIFY_STATIC (sizeof (max3421_ep_t ) == 12 , "size is not correct" );
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+
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typedef struct {
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// cached register
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uint8_t sndbc ;
@@ -325,7 +329,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
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static inline void hirq_write (uint8_t rhport , uint8_t data , bool in_isr ) {
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reg_write (rhport , HIRQ_ADDR , data , in_isr );
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// HIRQ write 1 is clear
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- _hcd_data .hirq &= ~data ;
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+ _hcd_data .hirq &= ( uint8_t ) ~data ;
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}
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static inline void hien_write (uint8_t rhport , uint8_t data , bool in_isr ) {
@@ -395,13 +399,13 @@ static void free_ep(uint8_t daddr) {
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}
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static max3421_ep_t * find_next_pending_ep (max3421_ep_t * cur_ep ) {
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- size_t const idx = cur_ep - _hcd_data .ep ;
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+ size_t const idx = ( size_t ) ( cur_ep - _hcd_data .ep ) ;
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// starting from next endpoint
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for (size_t i = idx + 1 ; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL ; i ++ ) {
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max3421_ep_t * ep = & _hcd_data .ep [i ];
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if (ep -> xfer_pending && ep -> packet_size ) {
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- // TU_LOG3("next pending i = %u\n", i);
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+ // TU_LOG3("next pending i = %u\r\ n", i);
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return ep ;
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}
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}
@@ -410,7 +414,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
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for (size_t i = 0 ; i <= idx ; i ++ ) {
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max3421_ep_t * ep = & _hcd_data .ep [i ];
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if (ep -> xfer_pending && ep -> packet_size ) {
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- // TU_LOG3("next pending i = %u\n", i);
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+ // TU_LOG3("next pending i = %u\r\ n", i);
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return ep ;
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}
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}
@@ -542,8 +546,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
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(void ) rhport ;
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(void ) daddr ;
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- uint8_t ep_num = tu_edpt_number (ep_desc -> bEndpointAddress );
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- uint8_t ep_dir = tu_edpt_dir (ep_desc -> bEndpointAddress );
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+ uint8_t const ep_num = tu_edpt_number (ep_desc -> bEndpointAddress );
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+ tusb_dir_t const ep_dir = tu_edpt_dir (ep_desc -> bEndpointAddress );
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max3421_ep_t * ep ;
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if (daddr == 0 && ep_num == 0 ) {
@@ -552,15 +556,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
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ep = allocate_ep ();
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TU_ASSERT (ep );
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ep -> daddr = daddr ;
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- ep -> ep_num = ep_num ;
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- ep -> ep_dir = ep_dir ;
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+ ep -> ep_num = ( uint8_t ) ( ep_num & 0x0f ) ;
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+ ep -> ep_dir = ( ep_dir == TUSB_DIR_IN ) ? 1 : 0 ;
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}
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if ( TUSB_XFER_ISOCHRONOUS == ep_desc -> bmAttributes .xfer ) {
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ep -> is_iso = 1 ;
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}
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- ep -> packet_size = tu_edpt_packet_size (ep_desc );
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+ ep -> packet_size = ( uint16_t ) ( tu_edpt_packet_size (ep_desc ) & 0x7ff );
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return true;
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}
@@ -582,7 +586,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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}
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sndbc_write (rhport , xact_len , in_isr );
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- uint8_t hxfr = ep -> ep_num | HXFR_OUT_NIN | (ep -> is_iso ? HXFR_ISO : 0 );
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+ uint8_t const hxfr = ( uint8_t ) ( ep -> ep_num | HXFR_OUT_NIN | (ep -> is_iso ? HXFR_ISO : 0 ) );
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hxfr_write (rhport , hxfr , in_isr );
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}
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@@ -595,7 +599,7 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
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reg_write (rhport , HCTL_ADDR , hctl , in_isr );
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}
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- uint8_t hxfr = ep -> ep_num | (ep -> is_iso ? HXFR_ISO : 0 );
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+ uint8_t const hxfr = ( uint8_t ) ( ep -> ep_num | (ep -> is_iso ? HXFR_ISO : 0 ) );
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hxfr_write (rhport , hxfr , in_isr );
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}
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@@ -628,13 +632,13 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
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// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
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bool hcd_edpt_xfer (uint8_t rhport , uint8_t daddr , uint8_t ep_addr , uint8_t * buffer , uint16_t buflen ) {
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const ep_dir = tu_edpt_dir (ep_addr );
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+ uint8_t const ep_dir = ( uint8_t ) tu_edpt_dir (ep_addr );
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max3421_ep_t * ep = find_opened_ep (daddr , ep_num , ep_dir );
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TU_VERIFY (ep );
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// control transfer can switch direction
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- ep -> ep_dir = ep_dir ;
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+ ep -> ep_dir = ep_dir ? 1u : 0u ;
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ep -> buf = buffer ;
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ep -> total_len = buflen ;
@@ -736,9 +740,9 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
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// However, since we are always in full speed mode, we can just check J-state
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if (jk == HRSL_KSTATUS ) {
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new_mode |= MODE_LOWSPEED ;
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- TU_LOG3 ("Low speed\n" );
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+ TU_LOG3 ("Low speed\r\ n" );
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}else {
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- TU_LOG3 ("Full speed\n" );
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+ TU_LOG3 ("Full speed\r\ n" );
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}
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new_mode |= MODE_SOFKAENAB ;
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mode_write (rhport , new_mode , in_isr );
@@ -758,9 +762,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
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// save data toggle
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if (ep -> ep_dir ) {
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- ep -> data_toggle = (hrsl & HRSL_RCVTOGRD ) ? 1 : 0 ;
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+ ep -> data_toggle = (hrsl & HRSL_RCVTOGRD ) ? 1u : 0u ;
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}else {
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- ep -> data_toggle = (hrsl & HRSL_SNDTOGRD ) ? 1 : 0 ;
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+ ep -> data_toggle = (hrsl & HRSL_SNDTOGRD ) ? 1u : 0u ;
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}
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ep -> xfer_pending = 0 ;
@@ -944,7 +948,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
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}
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// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
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- hirq &= ~HIRQ_SNDBAV_IRQ ;
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+ hirq &= ( uint8_t ) ~HIRQ_SNDBAV_IRQ ;
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if ( hirq ) {
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hirq_write (rhport , hirq , in_isr );
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}
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