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hathachhathach
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Merge pull request #351 from adafruit/update-tinyusb-0.16.0
update tinyusb to 0.16.0
2 parents 221ef2c + 7d72d0b commit 865f31b

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15 files changed

+150
-143
lines changed

15 files changed

+150
-143
lines changed

‎src/class/audio/audio_device.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -234,23 +234,23 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
234234
// Software encoding/decoding support FIFOs
235235
#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
236236
#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
237-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
237+
CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
238238
tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
239239
#if CFG_FIFO_MUTEX
240240
osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
241241
#endif
242242
#endif
243243

244244
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
245-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
245+
CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
246246
tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
247247
#if CFG_FIFO_MUTEX
248248
osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
249249
#endif
250250
#endif
251251

252252
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
253-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
253+
CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
254254
tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
255255
#if CFG_FIFO_MUTEX
256256
osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -260,23 +260,23 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
260260

261261
#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
262262
#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
263-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
263+
CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
264264
tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
265265
#if CFG_FIFO_MUTEX
266266
osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
267267
#endif
268268
#endif
269269

270270
#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
271-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
271+
CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
272272
tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
273273
#if CFG_FIFO_MUTEX
274274
osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
275275
#endif
276276
#endif
277277

278278
#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
279-
CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
279+
CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
280280
tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
281281
#if CFG_FIFO_MUTEX
282282
osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO

‎src/class/bth/bth_device.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,9 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
210210
request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
211211
{
212212
// HCI command packet addressing for single function Primary Controllers
213-
TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0);
213+
// also compatible with historical mode if enabled
214+
TU_VERIFY((request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0) ||
215+
(CFG_TUD_BTH_HISTORICAL_COMPATIBLE && request->bRequest == 0xe0));
214216
}
215217
else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
216218
{

‎src/class/bth/bth_device.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,17 @@
3636
#ifndef CFG_TUD_BTH_EVENT_EPSIZE
3737
#define CFG_TUD_BTH_EVENT_EPSIZE 16
3838
#endif
39+
3940
#ifndef CFG_TUD_BTH_DATA_EPSIZE
4041
#define CFG_TUD_BTH_DATA_EPSIZE 64
4142
#endif
4243

44+
// Allow BTH class to work in historically compatibility mode where the bRequest is always 0xe0.
45+
// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.2
46+
#ifndef CFG_TUD_BTH_HISTORICAL_COMPATIBLE
47+
#define CFG_TUD_BTH_HISTORICAL_COMPATIBLE 0
48+
#endif
49+
4350
typedef struct TU_ATTR_PACKED
4451
{
4552
uint16_t op_code;

‎src/class/cdc/cdc.h

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -182,21 +182,23 @@ typedef enum
182182
CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60,
183183
}cdc_management_request_t;
184184

185-
enum
186-
{
185+
enum {
187186
CDC_CONTROL_LINE_STATE_DTR = 0x01,
188187
CDC_CONTROL_LINE_STATE_RTS = 0x02,
189188
};
190189

191-
enum
192-
{
193-
CDC_LINE_CONDING_STOP_BITS_1 = 0, // 1 bit
194-
CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits
195-
CDC_LINE_CONDING_STOP_BITS_2 = 2, // 2 bits
190+
enum {
191+
CDC_LINE_CODING_STOP_BITS_1 = 0, // 1 bit
192+
CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
193+
CDC_LINE_CODING_STOP_BITS_2 = 2, // 2 bits
196194
};
197195

198-
enum
199-
{
196+
// TODO Backward compatible for typos. Maybe removed in the future release
197+
#define CDC_LINE_CONDING_STOP_BITS_1 CDC_LINE_CODING_STOP_BITS_1
198+
#define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
199+
#define CDC_LINE_CONDING_STOP_BITS_2 CDC_LINE_CODING_STOP_BITS_2
200+
201+
enum {
200202
CDC_LINE_CODING_PARITY_NONE = 0,
201203
CDC_LINE_CODING_PARITY_ODD = 1,
202204
CDC_LINE_CODING_PARITY_EVEN = 2,

‎src/class/cdc/cdc_host.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@
4444

4545
// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
4646
//#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM
47-
//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
47+
//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
4848
//#endif
4949

5050
// RX FIFO size

‎src/class/hid/hid_host.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,8 @@ typedef struct
7272
CFG_TUH_MEM_SECTION
7373
tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
7474

75+
tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
76+
7577
//--------------------------------------------------------------------+
7678
// Helper
7779
//--------------------------------------------------------------------+
@@ -216,6 +218,10 @@ static void set_protocol_complete(tuh_xfer_t* xfer)
216218
}
217219
}
218220

221+
void tuh_hid_set_default_protocol(uint8_t protocol) {
222+
_hidh_default_protocol = protocol;
223+
}
224+
219225
static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
220226
{
221227
TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol);
@@ -526,7 +532,7 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_
526532
p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength);
527533

528534
// Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
529-
p_hid->protocol_mode = HID_PROTOCOL_BOOT;
535+
p_hid->protocol_mode = _hidh_default_protocol;
530536
if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass )
531537
{
532538
p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
@@ -596,7 +602,7 @@ static void process_set_config(tuh_xfer_t* xfer)
596602
break;
597603

598604
case CONFIG_SET_PROTOCOL:
599-
_hidh_set_protocol(daddr, p_hid->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
605+
_hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC);
600606
break;
601607

602608
case CONFIG_GET_REPORT_DESC:

‎src/class/hid/hid_host.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,10 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
9797
// Application can use set_protocol() to switch back to Report protocol.
9898
uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx);
9999

100+
// Device by default is enumerated in Boot protocol for simplicity. Application
101+
// can use this to modify the default protocol for next enumeration.
102+
void tuh_hid_set_default_protocol(uint8_t protocol);
103+
100104
// Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
101105
// This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)
102106
bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);

‎src/common/tusb_mcu.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,10 @@
388388
#elif TU_CHECK_MCU(OPT_MCU_CH32V307)
389389
#define TUP_DCD_ENDPOINT_MAX 16
390390
#define TUP_RHPORT_HIGHSPEED 1
391+
392+
#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
393+
#define TUP_DCD_ENDPOINT_MAX 16
394+
#define TUP_RHPORT_HIGHSPEED 1
391395
#endif
392396

393397

‎src/device/dcd.h

Lines changed: 11 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -47,8 +47,7 @@
4747
// MACRO CONSTANT TYPEDEF PROTYPES
4848
//--------------------------------------------------------------------+
4949

50-
typedef enum
51-
{
50+
typedef enum {
5251
DCD_EVENT_INVALID = 0,
5352
DCD_EVENT_BUS_RESET,
5453
DCD_EVENT_UNPLUGGED,
@@ -65,13 +64,11 @@ typedef enum
6564
DCD_EVENT_COUNT
6665
} dcd_eventid_t;
6766

68-
typedef struct TU_ATTR_ALIGNED(4)
69-
{
67+
typedef struct TU_ATTR_ALIGNED(4) {
7068
uint8_t rhport;
7169
uint8_t event_id;
7270

73-
union
74-
{
71+
union {
7572
// BUS RESET
7673
struct {
7774
tusb_speed_t speed;
@@ -123,7 +120,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
123120
//--------------------------------------------------------------------+
124121

125122
// Initialize controller to device mode
126-
void dcd_init (uint8_t rhport);
123+
void dcd_init(uint8_t rhport);
127124

128125
// Interrupt Handler
129126
void dcd_int_handler(uint8_t rhport);
@@ -184,11 +181,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
184181
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
185182

186183
// Allocate packet buffer used by ISO endpoints
187-
// Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering
184+
// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
188185
TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
189186

190187
// Configure and enable an ISO endpoint according to descriptor
191-
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
188+
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
192189

193190
//--------------------------------------------------------------------+
194191
// Event API (implemented by stack)
@@ -198,32 +195,28 @@ TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t co
198195
extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
199196

200197
// helper to send bus signal event
201-
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
202-
{
198+
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) {
203199
dcd_event_t event = { .rhport = rhport, .event_id = eid };
204200
dcd_event_handler(&event, in_isr);
205201
}
206202

207203
// helper to send bus reset event
208-
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
209-
{
204+
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) {
210205
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
211206
event.bus_reset.speed = speed;
212207
dcd_event_handler(&event, in_isr);
213208
}
214209

215210
// helper to send setup received
216-
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
217-
{
211+
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) {
218212
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
219213
memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
220214

221215
dcd_event_handler(&event, in_isr);
222216
}
223217

224218
// helper to send transfer complete event
225-
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
226-
{
219+
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) {
227220
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
228221

229222
event.xfer_complete.ep_addr = ep_addr;
@@ -233,8 +226,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport
233226
dcd_event_handler(&event, in_isr);
234227
}
235228

236-
static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr)
237-
{
229+
TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) {
238230
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
239231
event.sof.frame_count = frame_count;
240232
dcd_event_handler(&event, in_isr);

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