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forgot to add fsdev_type.h
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/*
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* The MIT License (MIT)
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*
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* Copyright(c) N Conrad
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* Copyright(c) 2024, hathach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef TUSB_FSDEV_TYPE_H
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#define TUSB_FSDEV_TYPE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stdint.h"
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// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
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// Both of these MUST be a multiple of 2, and are in byte units.
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#ifndef FSDEV_BTABLE_BASE
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#define FSDEV_BTABLE_BASE 0U
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#endif
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TU_VERIFY_STATIC(FSDEV_BTABLE_BASE % 8 == 0, "BTABLE base must be aligned to 8 bytes");
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// FSDEV_PMA_SIZE is PMA buffer size in bytes.
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// - 512-byte devices, access with a stride of two words (use every other 16-bit address)
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// - 1024-byte devices, access with a stride of one word (use every 16-bit address)
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// - 2048-byte devices, access with 32-bit address
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// For purposes of accessing the packet
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#if FSDEV_PMA_SIZE == 512
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// 1x16 bit / word access scheme
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#define FSDEV_PMA_STRIDE 2
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#define pma_access_scheme TU_ATTR_ALIGNED(4)
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#elif FSDEV_PMA_SIZE == 1024
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// 2x16 bit / word access scheme
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#define FSDEV_PMA_STRIDE 1
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#define pma_access_scheme
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#elif FSDEV_PMA_SIZE == 2048
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// 32 bit access scheme
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#define FSDEV_BUS_32BIT
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#define FSDEV_PMA_STRIDE 1
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#define pma_access_scheme
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#endif
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// The fsdev_bus_t type can be used for both register and PMA access necessities
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#ifdef FSDEV_BUS_32BIT
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typedef uint32_t fsdev_bus_t;
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#define fsdevbus_unaligned_read(_addr) tu_unaligned_read32(_addr)
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#define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write32(_addr, _value)
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#else
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typedef uint16_t fsdev_bus_t;
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#define fsdevbus_unaligned_read(_addr) tu_unaligned_read16(_addr)
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#define fsdevbus_unaligned_write(_addr, _value) tu_unaligned_write16(_addr, _value)
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#endif
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enum {
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FSDEV_BUS_SIZE = sizeof(fsdev_bus_t),
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};
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//--------------------------------------------------------------------+
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// BTable Typedef
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//--------------------------------------------------------------------+
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enum {
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BTABLE_BUF_TX = 0,
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BTABLE_BUF_RX = 1
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};
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// hardware limit endpoint
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#define FSDEV_EP_COUNT 8
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// Buffer Table is located in Packet Memory Area (PMA) and therefore its address access is forced to either
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// 16-bit or 32-bit depending on FSDEV_BUS_32BIT.
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// 0: TX (IN), 1: RX (OUT)
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typedef union {
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// data is strictly 16-bit access (address could be 32-bit aligned)
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struct {
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volatile pma_access_scheme uint16_t addr;
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volatile pma_access_scheme uint16_t count;
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} ep16[FSDEV_EP_COUNT][2];
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// strictly 32-bit access
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struct {
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volatile uint32_t count_addr;
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} ep32[FSDEV_EP_COUNT][2];
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} fsdev_btable_t;
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TU_VERIFY_STATIC(sizeof(fsdev_btable_t) == FSDEV_EP_COUNT*8*FSDEV_PMA_STRIDE, "size is not correct");
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TU_VERIFY_STATIC(FSDEV_BTABLE_BASE + FSDEV_EP_COUNT*8 <= FSDEV_PMA_SIZE, "BTABLE does not fit in PMA RAM");
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#define FSDEV_BTABLE ((volatile fsdev_btable_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(FSDEV_BTABLE_BASE)))
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typedef struct {
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volatile pma_access_scheme fsdev_bus_t value;
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} fsdev_pma_buf_t;
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#define PMA_BUF_AT(_addr) ((fsdev_pma_buf_t*) (FSDEV_PMA_BASE + FSDEV_PMA_STRIDE*(_addr)))
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//--------------------------------------------------------------------+
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// Registers Typedef
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//--------------------------------------------------------------------+
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// volatile 32-bit aligned
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#define _va32 volatile TU_ATTR_ALIGNED(4)
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typedef struct {
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struct {
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_va32 fsdev_bus_t reg;
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}ep[FSDEV_EP_COUNT];
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_va32 uint32_t RESERVED7[8]; // Reserved
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_va32 fsdev_bus_t CNTR; // 40: Control register
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_va32 fsdev_bus_t ISTR; // 44: Interrupt status register
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_va32 fsdev_bus_t FNR; // 48: Frame number register
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_va32 fsdev_bus_t DADDR; // 4C: Device address register
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_va32 fsdev_bus_t BTABLE; // 50: Buffer Table address register (16-bit only)
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_va32 fsdev_bus_t LPMCSR; // 54: LPM Control and Status Register (32-bit only)
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_va32 fsdev_bus_t BCDR; // 58: Battery Charging Detector Register (32-bit only)
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} fsdev_regs_t;
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TU_VERIFY_STATIC(offsetof(fsdev_regs_t, CNTR) == 0x40, "Wrong offset");
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TU_VERIFY_STATIC(sizeof(fsdev_regs_t) == 0x5C, "Size is not correct");
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#define FSDEV_REG ((fsdev_regs_t*) FSDEV_REG_BASE)
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#ifndef USB_EPTX_STAT
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#define USB_EPTX_STAT 0x0030U
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#endif
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#ifndef USB_EPRX_STAT
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#define USB_EPRX_STAT 0x3000U
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#endif
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#ifndef USB_EPTX_STAT_Pos
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#define USB_EPTX_STAT_Pos 4u
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#endif
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#ifndef USB_EP_DTOG_TX_Pos
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#define USB_EP_DTOG_TX_Pos 6u
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#endif
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#ifndef USB_EP_CTR_TX_Pos
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#define USB_EP_CTR_TX_Pos 7u
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#endif
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typedef enum {
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EP_STAT_DISABLED = 0,
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EP_STAT_STALL = 1,
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EP_STAT_NAK = 2,
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EP_STAT_VALID = 3
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}ep_stat_t;
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#define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
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#define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
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//--------------------------------------------------------------------+
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// Endpoint Helper
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// - CTR is write 0 to clear
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// - DTOG and STAT are write 1 to toggle
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//--------------------------------------------------------------------+
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TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_read(uint32_t ep_id) {
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return FSDEV_REG->ep[ep_id].reg;
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}
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TU_ATTR_ALWAYS_INLINE static inline void ep_write(uint32_t ep_id, uint32_t value, bool need_exclusive) {
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if (need_exclusive) {
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dcd_int_disable(0);
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}
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FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
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if (need_exclusive) {
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dcd_int_enable(0);
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}
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}
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TU_ATTR_ALWAYS_INLINE static inline void ep_write_clear_ctr(uint32_t ep_id, tusb_dir_t dir) {
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uint32_t reg = FSDEV_REG->ep[ep_id].reg;
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reg |= USB_EP_CTR_TX | USB_EP_CTR_RX;
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reg &= USB_EPREG_MASK;
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reg &= ~(1 << (USB_EP_CTR_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
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ep_write(ep_id, reg, false);
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}
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TU_ATTR_ALWAYS_INLINE static inline void ep_change_status(uint32_t* reg, tusb_dir_t dir, ep_stat_t state) {
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*reg ^= (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
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}
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TU_ATTR_ALWAYS_INLINE static inline void ep_change_dtog(uint32_t* reg, tusb_dir_t dir, uint8_t state) {
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*reg ^= (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
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}
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TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(uint32_t reg) {
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return (reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
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}
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//--------------------------------------------------------------------+
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// BTable Helper
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//--------------------------------------------------------------------+
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TU_ATTR_ALWAYS_INLINE static inline uint32_t btable_get_addr(uint32_t ep_id, uint8_t buf_id) {
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#ifdef FSDEV_BUS_32BIT
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return FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr & 0x0000FFFFu;
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#else
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return FSDEV_BTABLE->ep16[ep_id][buf_id].addr;
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#endif
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}
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TU_ATTR_ALWAYS_INLINE static inline void btable_set_addr(uint32_t ep_id, uint8_t buf_id, uint16_t addr) {
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#ifdef FSDEV_BUS_32BIT
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uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
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count_addr = (count_addr & 0xFFFF0000u) | (addr & 0x0000FFFCu);
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FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
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#else
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FSDEV_BTABLE->ep16[ep_id][buf_id].addr = addr;
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#endif
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}
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TU_ATTR_ALWAYS_INLINE static inline uint16_t btable_get_count(uint32_t ep_id, uint8_t buf_id) {
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uint16_t count;
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#ifdef FSDEV_BUS_32BIT
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count = (FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr >> 16);
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#else
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count = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
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#endif
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return count & 0x3FFU;
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}
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TU_ATTR_ALWAYS_INLINE static inline void btable_set_count(uint32_t ep_id, uint8_t buf_id, uint16_t byte_count) {
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#ifdef FSDEV_BUS_32BIT
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uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
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count_addr = (count_addr & ~0x03FF0000u) | ((byte_count & 0x3FFu) << 16);
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FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
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#else
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uint16_t cnt = FSDEV_BTABLE->ep16[ep_id][buf_id].count;
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cnt = (cnt & ~0x3FFU) | (byte_count & 0x3FFU);
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FSDEV_BTABLE->ep16[ep_id][buf_id].count = cnt;
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#endif
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}
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/* Aligned buffer size according to hardware */
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TU_ATTR_ALWAYS_INLINE static inline uint16_t pma_align_buffer_size(uint16_t size, uint8_t* blsize, uint8_t* num_block) {
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/* The STM32 full speed USB peripheral supports only a limited set of
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* buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
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uint16_t block_in_bytes;
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if (size > 62) {
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block_in_bytes = 32;
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*blsize = 1;
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*num_block = tu_div_ceil(size, 32);
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} else {
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block_in_bytes = 2;
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*blsize = 0;
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*num_block = tu_div_ceil(size, 2);
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}
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return (*num_block) * block_in_bytes;
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}
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TU_ATTR_ALWAYS_INLINE static inline void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount) {
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uint8_t blsize, num_block;
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(void) pma_align_buffer_size(wCount, &blsize, &num_block);
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/* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
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uint16_t bl_nb = (blsize << 15) | ((num_block - blsize) << 10);
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if (bl_nb == 0) {
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// zlp but 0 is invalid value, set num_block to 1 (2 bytes)
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bl_nb = 1 << 10;
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}
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#ifdef FSDEV_BUS_32BIT
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uint32_t count_addr = FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr;
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count_addr = (bl_nb << 16) | (count_addr & 0x0000FFFFu);
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FSDEV_BTABLE->ep32[ep_id][buf_id].count_addr = count_addr;
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#else
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FSDEV_BTABLE->ep16[ep_id][buf_id].count = bl_nb;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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#endif

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