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ginkgmginkgm
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Merge branch 'feat/esp_flash_enable_s2_ut' into 'master'
esp_flash: fix several issues and enable unit test for ESP32-S2 Closes IDF-1409 See merge request espressif/esp-idf!8259
2 parents 3e8833c + 9e3b807 commit 6434c1e

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16 files changed

+92
-68
lines changed

16 files changed

+92
-68
lines changed

‎components/driver/test/test_spi_master.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1032,7 +1032,7 @@ TEST_CASE("spi_speed","[spi]")
10321032
for (int i = 0; i < TEST_TIMES; i++) {
10331033
ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
10341034
}
1035-
#ifndef CONFIG_SPIRAM_SUPPORT
1035+
#ifndef CONFIG_SPIRAM
10361036
TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
10371037
#endif
10381038

@@ -1049,7 +1049,7 @@ TEST_CASE("spi_speed","[spi]")
10491049
for (int i = 0; i < TEST_TIMES; i++) {
10501050
ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
10511051
}
1052-
#ifndef CONFIG_SPIRAM_SUPPORT
1052+
#ifndef CONFIG_SPIRAM
10531053
TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
10541054
#endif
10551055

@@ -1069,7 +1069,7 @@ TEST_CASE("spi_speed","[spi]")
10691069
for (int i = 0; i < TEST_TIMES; i++) {
10701070
ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
10711071
}
1072-
#ifndef CONFIG_SPIRAM_SUPPORT
1072+
#ifndef CONFIG_SPIRAM
10731073
TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
10741074
#endif
10751075

@@ -1085,7 +1085,7 @@ TEST_CASE("spi_speed","[spi]")
10851085
for (int i = 0; i < TEST_TIMES; i++) {
10861086
ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
10871087
}
1088-
#ifndef CONFIG_SPIRAM_SUPPORT
1088+
#ifndef CONFIG_SPIRAM
10891089
TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
10901090
#endif
10911091

‎components/idf_test/include/esp32/idf_performance_target.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,10 @@
1818
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30
1919
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27
2020

21+
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
22+
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000)
23+
#endif
24+
2125
// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
2226
#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70
2327
#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140

‎components/idf_test/include/esp32s2/idf_performance_target.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,7 @@
1616

1717
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
1818
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
19+
20+
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
21+
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1504*1000)
22+
#endif

‎components/idf_test/include/idf_performance.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -149,9 +149,7 @@
149149
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB
150150
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB (475*1000)
151151
#endif
152-
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB
153-
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000)
154-
#endif
152+
// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB in target file
155153
#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE
156154
#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600
157155
#endif

‎components/soc/include/hal/spi_flash_hal.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ typedef struct {
4848
/// Configuration structure for the SPI driver.
4949
typedef struct {
5050
spi_host_device_t host_id; ///< SPI peripheral ID.
51-
int cs_num; ///< Which cs pin is used, 0-2.
51+
int cs_num; ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1).
5252
bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
5353
int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
5454
esp_flash_speed_t speed;///< SPI flash clock speed to work at.

‎components/soc/soc/esp32s2/include/soc/spi_caps.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
#define SOC_SPI_PERIPH_NUM 3
1818
#define SOC_SPI_DMA_CHAN_NUM 3
19-
#define SOC_SPI_PERIPH_CS_NUM(i) 3
19+
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
2020

2121
#define SPI_FUNC_NUM 0
2222
#define SPI_IOMUX_PIN_NUM_HD 27

‎components/soc/src/esp32/include/hal/spi_flash_ll.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -238,9 +238,9 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
238238
*/
239239
static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
240240
{
241-
dev->pin.cs0_dis = (pin == 0) ? 0 : 1;
242-
dev->pin.cs1_dis = (pin == 1) ? 0 : 1;
243-
dev->pin.cs2_dis = (pin == 2) ? 0 : 1;
241+
dev->pin.cs0_dis = (pin != 0);
242+
dev->pin.cs1_dis = (pin != 1);
243+
dev->pin.cs2_dis = (pin != 2);
244244
}
245245

246246
/**

‎components/soc/src/esp32s2/include/hal/gpspi_flash_ll.h

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -185,8 +185,12 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
185185
*/
186186
static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
187187
{
188-
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
189-
dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
188+
dev->misc.cs0_dis = (pin != 0);
189+
dev->misc.cs1_dis = (pin != 1);
190+
dev->misc.cs2_dis = (pin != 2);
191+
dev->misc.cs3_dis = (pin != 3);
192+
dev->misc.cs4_dis = (pin != 4);
193+
dev->misc.cs5_dis = (pin != 5);
190194
}
191195

192196
/**
@@ -203,10 +207,10 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
203207
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
204208
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
205209

206-
// ctrl.val |= SPI_FAST_RD_MODE_M;
207210
switch (read_mode) {
208211
case SPI_FLASH_FASTRD:
209212
//the default option
213+
case SPI_FLASH_SLOWRD:
210214
break;
211215
case SPI_FLASH_QIO:
212216
ctrl.fread_quad = 1;
@@ -226,9 +230,6 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
226230
ctrl.fread_dual = 1;
227231
user.fwrite_dual = 1;
228232
break;
229-
// case SPI_FLASH_SLOWRD:
230-
// ctrl.fast_rd_mode = 0;
231-
// break;
232233
default:
233234
abort();
234235
}

‎components/soc/src/esp32s2/include/hal/spi_ll.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -576,6 +576,9 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
576576
hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1;
577577
hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1;
578578
hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1;
579+
hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1;
580+
hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1;
581+
hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1;
579582
}
580583

581584
/*------------------------------------------------------------------------------

‎components/soc/src/esp32s2/include/hal/spimem_flash_ll.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -227,12 +227,12 @@ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
227227
* Select which pin to use for the flash
228228
*
229229
* @param dev Beginning address of the peripheral registers.
230-
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
230+
* @param pin Pin ID to use, 0-1. Set to other values to disable all the CS pins.
231231
*/
232232
static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
233233
{
234-
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
235-
dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
234+
dev->misc.cs0_dis = (pin != 0);
235+
dev->misc.cs1_dis = (pin != 1);
236236
}
237237

238238
/**

‎components/soc/src/hal/spi_flash_hal.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <stdlib.h>
1616
#include "hal/spi_flash_hal.h"
1717
#include "string.h"
18+
#include "soc/spi_caps.h"
1819
#include "hal/hal_defs.h"
1920

2021
#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
@@ -68,6 +69,9 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_
6869
if (!esp_ptr_internal(data_out)) {
6970
return ESP_ERR_INVALID_ARG;
7071
}
72+
if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
73+
return ESP_ERR_INVALID_ARG;
74+
}
7175

7276
spi_flash_hal_clock_config_t clock_cfg = spi_flash_clk_cfg_reg[cfg->speed];
7377

‎components/spi_flash/esp_flash_spi_init.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -88,13 +88,10 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f
8888
//To avoid the panic caused by flash data line conflicts during cs line
8989
//initialization, disable the cache temporarily
9090
chip->os_func->start(chip->os_func_data);
91+
PIN_INPUT_ENABLE(iomux_reg);
9192
if (use_iomux) {
92-
// This requires `gpio_iomux_in` and `gpio_iomux_out` to be in the IRAM.
93-
// `linker.lf` is used fulfill this requirement.
94-
gpio_iomux_in(cs_io_num, spics_in);
95-
gpio_iomux_out(cs_io_num, spics_func, false);
93+
PIN_FUNC_SELECT(iomux_reg, spics_func);
9694
} else {
97-
PIN_INPUT_ENABLE(iomux_reg);
9895
if (cs_io_num < 32) {
9996
GPIO.enable_w1ts = (0x1 << cs_io_num);
10097
} else {

‎components/spi_flash/linker.lf

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,3 @@ entries:
77
spi_flash_chip_mxic (noflash)
88
spi_flash_chip_gd(noflash)
99
memspi_host_driver (noflash)
10-
11-
# `spi_bus_add_flash_device` uses these functions when the cache is disabled
12-
[mapping:driver_spiflash]
13-
archive: libdriver.a
14-
entries:
15-
gpio:gpio_iomux_out (noflash)
16-
gpio:gpio_iomux_in (noflash)

‎components/spi_flash/test/test_esp_flash.c

Lines changed: 47 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,10 @@ static uint8_t sector_buf[4096];
3131
#define TEST_SPI_READ_MODE SPI_FLASH_FASTRD
3232
// #define FORCE_GPIO_MATRIX
3333

34+
#if CONFIG_IDF_TARGET_ESP32
3435
#define EXTRA_SPI1_CLK_IO 17 //the pin which is usually used by the PSRAM clk
36+
#define SPI1_CS_IO 16 //the pin which is usually used by the PSRAM cs
3537

36-
#if CONFIG_IDF_TARGET_ESP32
3738
#define HSPI_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
3839
#define HSPI_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
3940
#define HSPI_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
@@ -47,28 +48,26 @@ static uint8_t sector_buf[4096];
4748
#define VSPI_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
4849
#define VSPI_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
4950
#define VSPI_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
51+
5052
#elif CONFIG_IDF_TARGET_ESP32S2
51-
#define FSPI_PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
52-
#define FSPI_PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
53-
#define FSPI_PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
54-
#define FSPI_PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
55-
#define FSPI_PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
56-
#define FSPI_PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
57-
58-
// Just use the same pins for HSPI and VSPI
53+
#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs
54+
#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd
55+
#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp
56+
57+
#define FSPI_PIN_NUM_MOSI 35
58+
#define FSPI_PIN_NUM_MISO 37
59+
#define FSPI_PIN_NUM_CLK 36
60+
#define FSPI_PIN_NUM_HD 33
61+
#define FSPI_PIN_NUM_WP 38
62+
#define FSPI_PIN_NUM_CS 34
63+
64+
// Just use the same pins for HSPI
5965
#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
6066
#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
6167
#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
6268
#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
6369
#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
6470
#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
65-
66-
#define VSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
67-
#define VSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
68-
#define VSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
69-
#define VSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
70-
#define VSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
71-
#define VSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
7271
#endif
7372

7473
#define TEST_CONFIG_NUM (sizeof(config_list)/sizeof(flashtest_config_t))
@@ -88,11 +87,10 @@ typedef void (*flash_test_func_t)(esp_flash_t* chip);
8887
8988
These tests run for all the flash chip configs shown in config_list, below (internal and external).
9089
*/
91-
#if defined(CONFIG_SPIRAM_SUPPORT) || TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
90+
#if defined(CONFIG_SPIRAM)
9291
#define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN)
9392
#define FLASH_TEST_CASE_3_IGNORE(STR, FUNCT_TO_RUN)
9493
#else
95-
// Disabled for ESP32-S2 due to lack of runners
9694
#define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \
9795
TEST_CASE(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, TEST_CONFIG_NUM);}
9896

@@ -110,14 +108,15 @@ static const char TAG[] = "test_esp_flash";
110108
{ \
111109
/* no need to init */ \
112110
.host_id = -1, \
113-
}, \
111+
} \
112+
, \
114113
{ \
115114
.io_mode = TEST_SPI_READ_MODE,\
116115
.speed = TEST_SPI_SPEED, \
117116
.host_id = SPI_HOST, \
118117
.cs_id = 1, \
119118
/* the pin which is usually used by the PSRAM */ \
120-
.cs_io_num = 16, \
119+
.cs_io_num = SPI1_CS_IO, \
121120
.input_delay_ns = 0, \
122121
}
123122

@@ -147,14 +146,14 @@ flashtest_config_t config_list[] = {
147146
flashtest_config_t config_list[] = {
148147
FLASHTEST_CONFIG_COMMON,
149148
/* No runners for esp32s2 for these config yet */
150-
// {
151-
// .io_mode = TEST_SPI_READ_MODE,
152-
// .speed = TEST_SPI_SPEED,
153-
// .host_id = FSPI_HOST,
154-
// .cs_id = 0,
155-
// .cs_io_num = FSPI_PIN_NUM_CS,
156-
// .input_delay_ns = 0,
157-
// },
149+
{
150+
.io_mode = TEST_SPI_READ_MODE,
151+
.speed = TEST_SPI_SPEED,
152+
.host_id = FSPI_HOST,
153+
.cs_id = 0,
154+
.cs_io_num = FSPI_PIN_NUM_CS,
155+
.input_delay_ns = 0,
156+
},
158157
// /* current runner doesn't have a flash on HSPI */
159158
// {
160159
// .io_mode = TEST_SPI_READ_MODE,
@@ -196,6 +195,19 @@ static void setup_bus(spi_host_device_t host_id)
196195
#ifdef EXTRA_SPI1_CLK_IO
197196
esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
198197
#endif
198+
199+
#if !DISABLED_FOR_TARGETS(ESP32)
200+
#if !CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_ESPTOOLPY_FLASHMODE_QOUT
201+
//Initialize the WP and HD pins, which are not automatically initialized on ESP32-S2.
202+
int wp_pin = spi_periph_signal[host_id].spiwp_iomux_pin;
203+
int hd_pin = spi_periph_signal[host_id].spihd_iomux_pin;
204+
gpio_iomux_in(wp_pin, spi_periph_signal[host_id].spiwp_in);
205+
gpio_iomux_out(wp_pin, spi_periph_signal[host_id].func, false);
206+
gpio_iomux_in(hd_pin, spi_periph_signal[host_id].spihd_in);
207+
gpio_iomux_out(hd_pin, spi_periph_signal[host_id].func, false);
208+
#endif //CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
209+
#endif //!DISABLED_FOR_TARGETS(ESP32)
210+
199211
#if !DISABLED_FOR_TARGETS(ESP32)
200212
} else if (host_id == FSPI_HOST) {
201213
ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1);
@@ -294,6 +306,11 @@ static void setup_new_chip(const flashtest_config_t* test_cfg, esp_flash_t** out
294306
TEST_ESP_OK(err);
295307
err = esp_flash_init(init_chip);
296308
TEST_ESP_OK(err);
309+
310+
uint32_t size;
311+
err = esp_flash_get_size(init_chip, &size);
312+
TEST_ESP_OK(err);
313+
ESP_LOGI(TAG, "Flash size: 0x%08X", size);
297314
*out_chip = init_chip;
298315
}
299316

@@ -679,17 +696,14 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash
679696
test_permutations(&config_list[0]);
680697
}
681698

682-
#ifndef CONFIG_SPIRAM_SUPPORT
683-
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
684-
// No runners
699+
#ifndef CONFIG_SPIRAM
685700
TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]")
686701
{
687702
for (int i = 0; i < TEST_CONFIG_NUM; i++) {
688703
test_permutations(&config_list[i]);
689704
}
690705
}
691706
#endif
692-
#endif
693707

694708
static void test_write_large_const_buffer(esp_flash_t* chip)
695709
{
@@ -867,7 +881,7 @@ static void test_flash_read_write_performance(esp_flash_t* chip)
867881

868882
TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_write, data_read, total_len);
869883

870-
#if !CONFIG_SPIRAM_SUPPORT && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
884+
#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
871885
# define CHECK_DATA(bus, suffix) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_##bus##suffix, "%d", speed_##suffix)
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# define CHECK_ERASE(bus, var) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_##bus##ERASE, "%d", var)
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#else

‎components/spi_flash/test/test_spi_flash.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ TEST_CASE("Test spi_flash read/write performance", "[spi_flash]")
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TEST_ASSERT_EQUAL_HEX8_ARRAY(data_to_write, data_read, total_len);
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// Data checks are disabled when PSRAM is used or in Freertos compliance check test
302-
#if !CONFIG_SPIRAM_SUPPORT && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
302+
#if !CONFIG_SPIRAM && !CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
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# define CHECK_DATA(suffix) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_##suffix, "%d", speed_##suffix)
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# define CHECK_ERASE(var) TEST_PERFORMANCE_GREATER_THAN(FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE, "%d", var)
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#else

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