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tannewttannewt
authored
Merge pull request #6437 from blues/7.3.x
swan_r5 improvements
2 parents 974ed8c + 321163d commit 67e9fb1

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9 files changed

+142
-38
lines changed

9 files changed

+142
-38
lines changed

‎ports/stm/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -302,11 +302,11 @@ $(BUILD)/firmware.hex: $(BUILD)/firmware.elf
302302

303303
$(BUILD)/firmware.uf2: $(BUILD)/firmware.hex
304304
$(ECHO) "Create $@"
305-
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f 0x57755a57 -b $(BOOTLOADER_OFFSET) -c -o "$(BUILD)/firmware.uf2" $^
305+
$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b $(BOOTLOADER_OFFSET) -c -o "$(BUILD)/firmware.uf2" $^
306306

307307
flash: $(BUILD)/firmware.bin
308308
$(ECHO) "Writing $< to the board"
309-
dfu-util -a 0 --dfuse-address 0x08000000 -D $(BUILD)/firmware.bin
309+
dfu-util -a 0 --dfuse-address $(BOOTLOADER_OFFSET) -D $(BUILD)/firmware.bin
310310

311311
include $(TOP)/py/mkrules.mk
312312

‎ports/stm/boards/STM32L4R5_boot.ld

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ MEMORY
88
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
99
FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
1010
FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 1024K-128K-64K-4K /* For now, limit to 1MB so that bank switching is still possible. */
11-
FLASH_FS (rw) : ORIGIN = 0x080e0000, LENGTH = 128K
11+
FLASH_FS (rw) : ORIGIN = 0x08100000, LENGTH = 1024K
1212
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
1313
}
1414

‎ports/stm/boards/STM32L4R5_default.ld

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ MEMORY
88
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
99
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
1010
FLASH_FIRMWARE (rx) : ORIGIN = 0x08001000, LENGTH = 1024K-128K-4K /* For now, limit to 1MB so that bank switching is still possible. */
11-
FLASH_FS (rw) : ORIGIN = 0x080e0000, LENGTH = 128K
11+
FLASH_FS (rw) : ORIGIN = 0x08100000, LENGTH = 1024K
1212
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
1313
}
1414

‎ports/stm/boards/swan_r5/board.c

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -33,14 +33,19 @@
3333
void initialize_discharge_pin(void) {
3434
/* Initialize the 3V3 discharge to be OFF and the output power to be ON */
3535
__HAL_RCC_GPIOE_CLK_ENABLE();
36+
__HAL_RCC_GPIOC_CLK_ENABLE();
37+
3638
GPIO_InitTypeDef GPIO_InitStruct;
37-
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
39+
/* Set the DISCHARGE pin and the USB_DETECT pin to FLOAT */
40+
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
3841
GPIO_InitStruct.Pull = GPIO_NOPULL;
39-
GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
4042
GPIO_InitStruct.Pin = GPIO_PIN_6;
41-
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
42-
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_6, GPIO_PIN_SET);
43+
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); /* PE6 DISCHRG */
44+
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* PC6 is USB_DETECT */
45+
46+
/* Turn on the 3V3 regulator */
4347
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
48+
GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
4449
GPIO_InitStruct.Pin = GPIO_PIN_4;
4550
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
4651
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_4, GPIO_PIN_SET);
@@ -53,14 +58,26 @@ void board_init(void) {
5358
// Set tick interrupt priority, default HAL value is intentionally invalid
5459
// Without this, USB does not function.
5560
HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
61+
62+
initialize_discharge_pin();
63+
64+
__HAL_RCC_GPIOE_CLK_ENABLE();
65+
GPIO_InitTypeDef GPIO_InitStruct;
66+
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
67+
GPIO_InitStruct.Pull = GPIO_NOPULL;
68+
GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
69+
GPIO_InitStruct.Pin = GPIO_PIN_2;
70+
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
71+
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_SET);
72+
HAL_Delay(50);
73+
HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, GPIO_PIN_RESET);
5674
}
5775

5876
bool board_requests_safe_mode(void) {
5977
return false;
6078
}
6179

6280
void reset_board(void) {
63-
initialize_discharge_pin();
6481
}
6582

6683
void board_deinit(void) {

‎ports/stm/boards/swan_r5/mpconfigboard.mk

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ LD_DEFAULT = boards/STM32L4R5_default.ld
1414
# UF2 boot option
1515
LD_BOOT = boards/STM32L4R5_boot.ld
1616
UF2_OFFSET = 0x8010000
17+
UF2_BOOTLOADER ?= 1
1718

1819
# Turn all of the below off while trying to get the thing to run
1920
# These modules are implemented in ports/<port>/common-hal:

‎ports/stm/boards/swan_r5/pins.c

Lines changed: 102 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,49 +1,131 @@
11
#include "py/objtuple.h"
22
#include "shared-bindings/board/__init__.h"
33

4+
// extended pins
5+
STATIC const mp_rom_map_elem_t board_module_carrier_table[] = {
6+
{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PD09) },
7+
{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PD08) },
8+
{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) },
9+
{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) },
10+
{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PE03) },
11+
12+
{ MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PD01) },
13+
{ MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) },
14+
{ MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) },
15+
{ MP_ROM_QSTR(MP_QSTR_CS), MP_ROM_PTR(&pin_PD00) },
16+
17+
{ MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_PTR(&pin_PG12) },
18+
{ MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_PTR(&pin_PB04) },
19+
{ MP_ROM_QSTR(MP_QSTR_RX0), MP_ROM_PTR(&pin_PG08) },
20+
{ MP_ROM_QSTR(MP_QSTR_TX0), MP_ROM_PTR(&pin_PG07) },
21+
22+
{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
23+
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
24+
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
25+
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) },
26+
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) },
27+
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) },
28+
{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) },
29+
{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) },
30+
{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) },
31+
{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PE01) },
32+
33+
{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },
34+
{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },
35+
{ MP_ROM_QSTR(MP_QSTR_SCL3), MP_ROM_PTR(&pin_PC00) },
36+
{ MP_ROM_QSTR(MP_QSTR_SDA3), MP_ROM_PTR(&pin_PC09) },
37+
38+
{ MP_ROM_QSTR(MP_QSTR_RX2), MP_ROM_PTR(&pin_PD06) },
39+
{ MP_ROM_QSTR(MP_QSTR_RTS2), MP_ROM_PTR(&pin_PD04) },
40+
{ MP_ROM_QSTR(MP_QSTR_CTS2), MP_ROM_PTR(&pin_PD03) },
41+
{ MP_ROM_QSTR(MP_QSTR_TX3), MP_ROM_PTR(&pin_PB10) },
42+
{ MP_ROM_QSTR(MP_QSTR_RX3), MP_ROM_PTR(&pin_PB11) },
43+
{ MP_ROM_QSTR(MP_QSTR_RTS3), MP_ROM_PTR(&pin_PD02) },
44+
{ MP_ROM_QSTR(MP_QSTR_CTS3), MP_ROM_PTR(&pin_PB13) },
45+
46+
{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
47+
{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
48+
{ MP_ROM_QSTR(MP_QSTR_SCL2), MP_ROM_PTR(&pin_PF01) },
49+
{ MP_ROM_QSTR(MP_QSTR_SDA2), MP_ROM_PTR(&pin_PF00) },
50+
51+
{ MP_ROM_QSTR(MP_QSTR_QEN), MP_ROM_PTR(&pin_PD05) },
52+
{ MP_ROM_QSTR(MP_QSTR_QCS), MP_ROM_PTR(&pin_PC11) },
53+
{ MP_ROM_QSTR(MP_QSTR_QCLK), MP_ROM_PTR(&pin_PE10) },
54+
55+
{ MP_ROM_QSTR(MP_QSTR_EN), MP_ROM_PTR(&pin_PE04) },
56+
{ MP_ROM_QSTR(MP_QSTR_TX2), MP_ROM_PTR(&pin_PA02) },
57+
{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) },
58+
{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
59+
{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
60+
{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) },
61+
{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
62+
{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) },
63+
{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) },
64+
65+
{ MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },
66+
{ MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },
67+
{ MP_ROM_QSTR(MP_QSTR_QIO3), MP_ROM_PTR(&pin_PE15) },
68+
{ MP_ROM_QSTR(MP_QSTR_QIO2), MP_ROM_PTR(&pin_PE14) },
69+
{ MP_ROM_QSTR(MP_QSTR_QIO1), MP_ROM_PTR(&pin_PB00) },
70+
{ MP_ROM_QSTR(MP_QSTR_QIO0), MP_ROM_PTR(&pin_PE12) },
71+
72+
};
73+
74+
MP_DEFINE_CONST_DICT(board_module_carrier, board_module_carrier_table);
75+
76+
const mp_obj_type_t carrier_type = {
77+
{ &mp_type_type },
78+
.name = MP_QSTR_Ext,
79+
.locals_dict = (mp_obj_dict_t *)&board_module_carrier,
80+
};
81+
82+
483
// Core Feather Pins
584
STATIC const mp_rom_map_elem_t board_module_globals_table[] = {
685
CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
786

87+
{ MP_ROM_QSTR(MP_QSTR_ext), MP_ROM_PTR(&carrier_type) },
88+
889
{ MP_ROM_QSTR(MP_QSTR_ENABLE_3V3), MP_ROM_PTR(&pin_PE04) },
990
{ MP_ROM_QSTR(MP_QSTR_DISCHARGE_3V3), MP_ROM_PTR(&pin_PE06) },
1091
{ MP_ROM_QSTR(MP_QSTR_DISABLE_DISCHARGING), MP_ROM_TRUE },
1192
{ MP_ROM_QSTR(MP_QSTR_ENABLE_DISCHARGING), MP_ROM_FALSE },
1293

13-
{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) },
14-
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) },
15-
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) },
16-
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) },
17-
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) },
18-
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) },
94+
{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, // PWM, ADC
95+
{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PA01) }, // PWM, ADC
96+
{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, // ADC
97+
{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PC01) }, // ADC
98+
{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC04) }, // ADC
99+
{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PC05) }, // ADC
100+
19101
{ MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_PA00) },
20102
{ MP_ROM_QSTR(MP_QSTR_BUTTON_USR), MP_ROM_PTR(&pin_PC13) },
21103
{ MP_ROM_QSTR(MP_QSTR_SWITCH), MP_ROM_PTR(&pin_PE04) },
22-
{ MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) }, // boot button, but looks like it's wired to GND on the schematic
104+
{ MP_ROM_QSTR(MP_QSTR_BUTTON), MP_ROM_PTR(&pin_PB02) },
23105

24-
{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) },
25-
{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) },
26-
{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) },
27-
{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) }, // DAC1 output also
28-
{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) },
29-
{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) },
106+
{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, // PWM
107+
{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, // PWM
108+
{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, // PWM
109+
{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA04) }, // ADC, DAC1 output also
110+
{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, // ADC, PWM
111+
{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, // ADC, PWM
30112

31113
{ MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PE02) },
32-
{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, // DAC1 output also
114+
{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, // ADC, PWM, DAC2 output also
33115

34-
{ MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) },
35-
{ MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) },
116+
{ MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB07) }, // PWM
117+
{ MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB06) }, // PWM
36118

37119
{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, // D10
38120
{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, // D13
39121

40122
{ MP_ROM_QSTR(MP_QSTR_SS), MP_ROM_PTR(&pin_PD00) },
41123
{ MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PD01) },
42-
{ MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) },
43-
{ MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) },
124+
{ MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PB14) }, // PWM?
125+
{ MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB15) }, // PWM?
44126

45-
{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) },
46-
{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) },
127+
{ MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA09) }, // ADC, PWM
128+
{ MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA10) }, // PWM
47129

48130
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
49131
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },

‎ports/stm/mpconfigport.mk

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F405xx STM32F407xx))
88
CIRCUITPY_SDIOIO ?= 1
99
# Number of USB endpoint pairs.
1010
USB_NUM_ENDPOINT_PAIRS = 4
11+
UF2_FAMILY_ID ?= 0x6d0922fa
1112
endif
1213

1314
ifeq ($(MCU_SERIES),F4)
@@ -25,6 +26,7 @@ ifeq ($(MCU_SERIES),F4)
2526
CIRCUITPY_ROTARYIO ?= 0
2627
CIRCUITPY_RTC ?= 0
2728
USB_NUM_ENDPOINT_PAIRS = 4
29+
UF2_FAMILY_ID ?= 0x57755a57
2830
endif
2931

3032
ifeq ($(MCU_SERIES),H7)
@@ -43,6 +45,7 @@ ifeq ($(MCU_SERIES),H7)
4345
CIRCUITPY_RTC ?= 0
4446

4547
USB_NUM_ENDPOINT_PAIRS = 9
48+
UF2_FAMILY_ID ?= 0x6db66082
4649
endif
4750

4851
ifeq ($(MCU_SERIES),F7)
@@ -59,6 +62,7 @@ ifeq ($(MCU_SERIES),F7)
5962
CIRCUITPY_RTC ?= 0
6063

6164
USB_NUM_ENDPOINT_PAIRS = 6
65+
UF2_FAMILY_ID ?= 0x53b80f00
6266
endif
6367

6468
ifeq ($(MCU_SERIES),L4)
@@ -77,6 +81,7 @@ ifeq ($(MCU_SERIES),L4)
7781
# This slide deck https://www.st.com/content/ccc/resource/training/technical/product_training/98/89/c8/6c/3e/e9/49/79/STM32L4_Peripheral_USB.pdf/files/STM32L4_Peripheral_USB.pdf/jcr:content/translations/en.STM32L4_Peripheral_USB.pdf
7882
# cites 16 endpoints, 8 endpoint pairs, while section 3.39 of the L4R5 datasheet states 6 endpoint pairs.
7983
USB_NUM_ENDPOINT_PAIRS = 6
84+
UF2_FAMILY_ID ?= 0x00ff6919
8085
endif
8186

8287
CIRCUITPY_PARALLELDISPLAY := 0

‎ports/stm/supervisor/internal_flash.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -95,12 +95,8 @@ STATIC const flash_layout_t flash_layout[] = {
9595
STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
9696

9797
#elif defined(STM32L4)
98-
// todo - the L4 devices can have different flash sizes and different page sizes
99-
// depending upon the dual bank configuration
100-
// This is hardcoded for the Swan R5. When support for other devices is needed more conditionals will be required
101-
// to differentiate.
10298
STATIC const flash_layout_t flash_layout[] = {
103-
{ 0x08000000, 0x1000, 256 },
99+
{ 0x08100000, 0x1000, 256 },
104100
};
105101
STATIC uint8_t _flash_cache[0x1000] __attribute__((aligned(4)));
106102

@@ -174,6 +170,9 @@ uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *si
174170
}
175171

176172
void supervisor_flash_init(void) {
173+
#ifdef STM32L4
174+
// todo - check that the device is in dual bank mode
175+
#endif
177176
}
178177

179178
uint32_t supervisor_flash_get_block_size(void) {
@@ -202,7 +201,7 @@ void port_internal_flash_flush(void) {
202201
FLASH_EraseInitTypeDef EraseInitStruct = {};
203202
#if CPY_STM32L4
204203
EraseInitStruct.TypeErase = TYPEERASE_PAGES;
205-
EraseInitStruct.Banks = FLASH_BANK_1;
204+
EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode
206205
#else
207206
EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
208207
EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V

‎ports/stm/supervisor/internal_flash.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -97,9 +97,9 @@
9797
#endif
9898

9999
#ifdef STM32L4R5xx
100-
#define STM32_FLASH_SIZE 0x100000 // 1MB // for now just use the first bank
101-
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 // 128KiB
102-
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x080e0000
100+
#define STM32_FLASH_SIZE 0x200000 // 2MB
101+
#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x100000 // 1024KiB
102+
#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08100000
103103
#endif
104104

105105
#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE)

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