Read fuses to know what flash and ram pins to never reset

Author: tannewt

ports/espressif/Makefile

@@ -98,6 +98,8 @@ INC += \
 	-isystem esp-idf/components/bt/host/nimble/port/include \
 	-isystem esp-idf/components/driver/include \
 	-isystem esp-idf/components/driver/$(IDF_TARGET)/include \
+	-isystem esp-idf/components/efuse/include \
+	-isystem esp-idf/components/efuse/$(IDF_TARGET)/include \
 	-isystem esp-idf/components/$(IDF_TARGET)/include \
 	-isystem esp-idf/components/esp_adc_cal/include \
 	-isystem esp-idf/components/esp_common/include \

ports/espressif/boards/adafruit_qtpy_esp32_pico/mpconfigboard.mk

@@ -1,5 +1,5 @@
 CIRCUITPY_CREATOR_ID =  0x0000239A
-CIRCUITPY_CREATION_ID = 0x00320002
+CIRCUITPY_CREATION_ID = 0x00320003
 
 IDF_TARGET = esp32
 

ports/espressif/common-hal/microcontroller/Pin.c

@@ -46,17 +46,7 @@ static const uint64_t pin_mask_reset_forbidden =
     // Never ever reset serial pins for bootloader and possibly USB-serial converter.
     GPIO_SEL_1 |          // TXD0
     GPIO_SEL_3 |          // RXD0
-    // Never ever reset pins used to communicate with SPI flash and PSRAM.
-    GPIO_SEL_6 |          // CLK
-    GPIO_SEL_7 |
-    GPIO_SEL_8 |
-    GPIO_SEL_9 |          // (PSRAM) SD2
-    GPIO_SEL_10 |         // (PSRAM) SD3
-    GPIO_SEL_11 |         // CMD
-    GPIO_SEL_16 |         // SPIHD
-    GPIO_SEL_17 |         // SPIDO
-    GPIO_SEL_18 |         // SPIWP
-    GPIO_SEL_23 |         // SPIDI
+    // SPI flash and PSRAM pins are protected at runtime in supervisor/port.c.
     #endif // ESP32
 
     #if defined(CONFIG_IDF_TARGET_ESP32C3)

ports/espressif/supervisor/port.c

@@ -81,11 +81,19 @@
 #include "soc/cache_memory.h"
 #endif
 
+#include "soc/efuse_reg.h"
 #include "soc/rtc_cntl_reg.h"
 
 #include "esp_debug_helpers.h"
 
+#include "bootloader_flash_config.h"
+#include "esp_efuse.h"
 #include "esp_ipc.h"
+#include "esp_rom_efuse.h"
+
+#ifdef CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/efuse.h"
+#endif
 
 #ifdef CONFIG_SPIRAM
 #include "esp32/spiram.h"
@@ -134,6 +142,93 @@ STATIC void tick_timer_cb(void *arg) {
 
 void sleep_timer_cb(void *arg);
 
+// The ESP-IDF determines these pins at runtime so we do too. This code is based on:
+// https://github.com/espressif/esp-idf/blob/6d85d53ceec30c818a92c2fff8f5437d21c4720f/components/esp_hw_support/port/esp32/spiram_psram.c#L810
+// IO-pins for PSRAM.
+// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
+// hardcode the flash pins as well, making this code incompatible with either a setup
+// that has the flash on non-standard pins or ESP32s with built-in flash.
+#define PSRAM_SPIQ_SD0_IO          7
+#define PSRAM_SPID_SD1_IO          8
+#define PSRAM_SPIWP_SD3_IO         10
+#define PSRAM_SPIHD_SD2_IO         9
+
+#define FLASH_HSPI_CLK_IO          14
+#define FLASH_HSPI_CS_IO           15
+#define PSRAM_HSPI_SPIQ_SD0_IO     12
+#define PSRAM_HSPI_SPID_SD1_IO     13
+#define PSRAM_HSPI_SPIWP_SD3_IO    2
+#define PSRAM_HSPI_SPIHD_SD2_IO    4
+
+// PSRAM clock and cs IO should be configured based on hardware design.
+// For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the cs IO is IO16,
+// they are the default value for these two configs.
+#define D0WD_PSRAM_CLK_IO          CONFIG_D0WD_PSRAM_CLK_IO  // Default value is 17
+#define D0WD_PSRAM_CS_IO           CONFIG_D0WD_PSRAM_CS_IO   // Default value is 16
+
+#define D2WD_PSRAM_CLK_IO          CONFIG_D2WD_PSRAM_CLK_IO  // Default value is 9
+#define D2WD_PSRAM_CS_IO           CONFIG_D2WD_PSRAM_CS_IO   // Default value is 10
+
+// There is no reason to change the pin of an embedded psram.
+// So define the number of pin directly, instead of configurable.
+#define D0WDR2_V3_PSRAM_CLK_IO    6
+#define D0WDR2_V3_PSRAM_CS_IO     16
+
+// For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
+#define PICO_PSRAM_CLK_IO          6
+#define PICO_PSRAM_CS_IO           CONFIG_PICO_PSRAM_CS_IO   // Default value is 10
+
+#define PICO_V3_02_PSRAM_CLK_IO    10
+#define PICO_V3_02_PSRAM_CS_IO     9
+
+static void _never_reset_spi_ram_flash(void) {
+    #if defined(CONFIG_IDF_TARGET_ESP32)
+    uint32_t pkg_ver = esp_efuse_get_pkg_ver();
+    if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
+        never_reset_pin_number(D2WD_PSRAM_CLK_IO);
+        never_reset_pin_number(D2WD_PSRAM_CS_IO);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && esp_efuse_get_chip_ver() >= 3) {
+        // This chip is ESP32-PICO-V3 and doesn't have PSRAM.
+    } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
+        never_reset_pin_number(PICO_PSRAM_CLK_IO);
+        never_reset_pin_number(PICO_PSRAM_CS_IO);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
+        never_reset_pin_number(PICO_V3_02_PSRAM_CLK_IO);
+        never_reset_pin_number(PICO_V3_02_PSRAM_CS_IO);
+    } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)) {
+        never_reset_pin_number(D0WD_PSRAM_CLK_IO);
+        never_reset_pin_number(D0WD_PSRAM_CS_IO);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3) {
+        never_reset_pin_number(D0WDR2_V3_PSRAM_CLK_IO);
+        never_reset_pin_number(D0WDR2_V3_PSRAM_CS_IO);
+    }
+
+    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+    if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
+        never_reset_pin_number(SPI_IOMUX_PIN_NUM_CLK);
+        never_reset_pin_number(SPI_IOMUX_PIN_NUM_CS);
+        never_reset_pin_number(PSRAM_SPIQ_SD0_IO);
+        never_reset_pin_number(PSRAM_SPID_SD1_IO);
+        never_reset_pin_number(PSRAM_SPIWP_SD3_IO);
+        never_reset_pin_number(PSRAM_SPIHD_SD2_IO);
+    } else if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
+        never_reset_pin_number(FLASH_HSPI_CLK_IO);
+        never_reset_pin_number(FLASH_HSPI_CS_IO);
+        never_reset_pin_number(PSRAM_HSPI_SPIQ_SD0_IO);
+        never_reset_pin_number(PSRAM_HSPI_SPID_SD1_IO);
+        never_reset_pin_number(PSRAM_HSPI_SPIWP_SD3_IO);
+        never_reset_pin_number(PSRAM_HSPI_SPIHD_SD2_IO);
+    } else {
+        never_reset_pin_number(EFUSE_SPICONFIG_RET_SPICLK(spiconfig));
+        never_reset_pin_number(EFUSE_SPICONFIG_RET_SPICS0(spiconfig));
+        never_reset_pin_number(EFUSE_SPICONFIG_RET_SPIQ(spiconfig));
+        never_reset_pin_number(EFUSE_SPICONFIG_RET_SPID(spiconfig));
+        never_reset_pin_number(EFUSE_SPICONFIG_RET_SPIHD(spiconfig));
+        never_reset_pin_number(bootloader_flash_get_wp_pin());
+    }
+    #endif
+}
+
 safe_mode_t port_init(void) {
     esp_timer_create_args_t args;
     args.callback = &tick_timer_cb;
@@ -214,6 +309,8 @@ safe_mode_t port_init(void) {
     }
     #endif
 
+    _never_reset_spi_ram_flash();
+
     if (heap == NULL) {
         size_t heap_total = heap_caps_get_total_size(MALLOC_CAP_8BIT);
         heap_size = MIN(heap_caps_get_largest_free_block(MALLOC_CAP_8BIT), heap_total / 2);