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mimxrt10xx: Add pin tables for the SAI peripheral (1011 only)
1 parent edbcf11 commit 80b758f

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3 files changed

+81
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ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c

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@@ -166,3 +166,41 @@ const mcu_pwm_obj_t mcu_pwm_list[20] = {
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PWM_PIN(PWM1, kPWM_Module_3, kPWM_PwmX, IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X, &pin_GPIO_AD_09),
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};
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const mcu_sai_obj_t mcu_sai_mclk_list[2] = {
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SAI_PIN(IOMUXC_GPIO_08_SAI1_MCLK, 1, 0, &pin_GPIO_08),
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SAI_PIN(IOMUXC_GPIO_00_SAI3_MCLK, 3, 0, &pin_GPIO_00),
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};
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const mcu_sai_obj_t mcu_sai_rx_bclk_list[4] = {
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SAI_PIN(IOMUXC_GPIO_SD_13_SAI3_RX_BCLK, 3, 0, &pin_GPIO_SD_13),
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SAI_PIN(IOMUXC_GPIO_SD_01_SAI3_TX_BCLK, 3, 0, &pin_GPIO_SD_01),
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SAI_PIN(IOMUXC_GPIO_06_SAI1_TX_BCLK, 1, 0, &pin_GPIO_SD_06),
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SAI_PIN(IOMUXC_GPIO_01_SAI1_RX_BCLK, 1, 0, &pin_GPIO_SD_13),
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};
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const mcu_sai_obj_t mcu_sai_rx_data_list[2] = {
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SAI_PIN(IOMUXC_GPIO_SD_03_SAI3_RX_DATA, 3, 0, &pin_GPIO_SD_03),
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SAI_PIN(IOMUXC_GPIO_03_SAI1_RX_DATA00, 1, 0, &pin_GPIO_03),
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};
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const mcu_sai_obj_t mcu_sai_rx_sync_list[2] = {
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SAI_PIN(IOMUXC_GPIO_SD_04_SAI3_RX_SYNC, 3, 0, &pin_GPIO_SD_04),
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SAI_PIN(IOMUXC_GPIO_02_SAI1_RX_SYNC, 1, 0, &pin_GPIO_02),
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};
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const mcu_sai_obj_t mcu_sai_tx_bclk_list[2] = {
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SAI_PIN(IOMUXC_GPIO_SD_01_SAI3_TX_BCLK, 3, 0, &pin_GPIO_SD_01),
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SAI_PIN(IOMUXC_GPIO_06_SAI1_TX_BCLK, 1, 0, &pin_GPIO_06),
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};
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const mcu_sai_obj_t mcu_sai_tx_data_list[3] = {
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SAI_PIN(IOMUXC_GPIO_SD_02_SAI3_TX_DATA, 3, 0, &pin_GPIO_SD_02),
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SAI_PIN(IOMUXC_GPIO_05_SAI1_TX_DATA01, 1, 1, &pin_GPIO_05),
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SAI_PIN(IOMUXC_GPIO_04_SAI1_TX_DATA00, 1, 0, &pin_GPIO_04),
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};
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const mcu_sai_obj_t mcu_sai_tx_sync_list[2] = {
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SAI_PIN(IOMUXC_GPIO_SD_00_SAI3_TX_SYNC, 3, 0, &pin_GPIO_SD_00),
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SAI_PIN(IOMUXC_GPIO_07_SAI1_TX_SYNC, 1, 0, &pin_GPIO_07),
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};

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h

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@@ -47,4 +47,12 @@ extern const mcu_periph_obj_t mcu_uart_cts_list[4];
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extern const mcu_pwm_obj_t mcu_pwm_list[20];
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extern const mcu_sai_obj_t mcu_sai_mclk_list[2];
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extern const mcu_sai_obj_t mcu_sai_rx_bclk_list[4];
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extern const mcu_sai_obj_t mcu_sai_rx_data_list[2];
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extern const mcu_sai_obj_t mcu_sai_rx_sync_list[2];
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extern const mcu_sai_obj_t mcu_sai_tx_bclk_list[2];
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extern const mcu_sai_obj_t mcu_sai_tx_data_list[3];
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extern const mcu_sai_obj_t mcu_sai_tx_sync_list[2];
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#endif // MICROPY_INCLUDED_MIMXRT10XX_MIMXRT1011_PERIPHERALS_MIMXRT1011_PERIPH_H

ports/mimxrt10xx/peripherals/mimxrt10xx/periph.h

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@@ -72,6 +72,41 @@ typedef struct {
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.pin = p_pin, \
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}
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#define IOMUXC_MUXREGISTER(x) IOMUXC_MUXREGISTER_(x)
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#define IOMUXC_MUXREGISTER_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_muxregister
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#define IOMUXC_MUX_MODE(x) IOMUXC_MUX_MODE_(x)
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#define IOMUXC_MUX_MODE_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_mux_mode
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#define IOMUXC_INPUT_REGISTER(x) IOMUXC_INPUT_REGISTER_(x)
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#define IOMUXC_INPUT_REGISTER_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_input_register
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#define IOMUXC_INPUT_IDX(x) IOMUXC_INPUT_IDX_(x)
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#define IOMUXC_INPUT_IDX_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_input_idx
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#define IOMUXC_CONFIG_REG(x) IOMUXC_CONFIG_REG_(x)
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#define IOMUXC_CONFIG_REG_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_config_reg
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#define IOMUXC_PIN(x) IOMUXC_PIN_(x)
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#define IOMUXC_PIN_(p_muxregister, p_mux_mode, p_input_register, p_input_idx, p_config_reg, p_pin) p_pin
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typedef struct {
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uint8_t sai;
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uint8_t channel;
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uint8_t mux_mode;
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uint8_t input_idx;
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uint32_t input_reg;
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const mcu_pin_obj_t *pin;
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} mcu_sai_obj_t;
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#define SAI_PIN(p_iomuxc, p_sai, p_channel, p_pin) \
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SAI_PIN_(p_iomuxc, p_sai, p_channel, p_pin)
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#define SAI_PIN_(p_mux_reg, p_mux_mode, p_input_reg, p_input_idx, p_config_reg, p_sai, p_channel, p_pin) \
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{ \
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.sai = p_sai, \
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.channel = p_channel, \
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.mux_mode = p_mux_mode, \
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.input_reg = p_input_reg, \
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.input_idx = p_input_idx, \
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.pin = p_pin, \
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}
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extern LPI2C_Type *mcu_i2c_banks[];
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extern LPSPI_Type *mcu_spi_banks[];
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extern LPUART_Type *mcu_uart_banks[];

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