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tannewttannewt
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Merge pull request #3425 from jepler/canbus
canio: Initial implementation for SAM E5x MCUs
2 parents 9f892cd + 82f37c9 commit 98185e9

40 files changed

+2963
-40
lines changed

‎locale/circuitpython.pot

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ msgid ""
88
msgstr ""
99
"Project-Id-Version: PACKAGE VERSION\n"
1010
"Report-Msgid-Bugs-To: \n"
11-
"POT-Creation-Date: 2020-09-16 17:07-0700\n"
11+
"POT-Creation-Date: 2020-09-21 16:45-0500\n"
1212
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
1313
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
1414
"Language-Team: LANGUAGE <[email protected]>\n"
@@ -92,7 +92,11 @@ msgstr ""
9292
msgid "%q must be a tuple of length 2"
9393
msgstr ""
9494

95-
#: ports/atmel-samd/common-hal/sdioio/SDCard.c
95+
#: shared-bindings/canio/Match.c
96+
msgid "%q out of range"
97+
msgstr ""
98+
99+
#: ports/atmel-samd/common-hal/microcontroller/Pin.c
96100
msgid "%q pin invalid"
97101
msgstr ""
98102

@@ -280,6 +284,10 @@ msgstr ""
280284
msgid "All I2C peripherals are in use"
281285
msgstr ""
282286

287+
#: ports/atmel-samd/common-hal/canio/Listener.c
288+
msgid "All RX FIFOs in use"
289+
msgstr ""
290+
283291
#: ports/nrf/common-hal/busio/SPI.c
284292
msgid "All SPI peripherals are in use"
285293
msgstr ""
@@ -316,6 +324,10 @@ msgstr ""
316324
msgid "Already advertising."
317325
msgstr ""
318326

327+
#: ports/atmel-samd/common-hal/canio/Listener.c
328+
msgid "Already have all-matches listener"
329+
msgstr ""
330+
319331
#: shared-module/memorymonitor/AllocationAlarm.c
320332
#: shared-module/memorymonitor/AllocationSize.c
321333
msgid "Already running"
@@ -752,7 +764,7 @@ msgstr ""
752764
msgid "Error in regex"
753765
msgstr ""
754766

755-
#: shared-bindings/_bleio/__init__.c shared-bindings/aesio/aes.c
767+
#: py/enum.c shared-bindings/_bleio/__init__.c shared-bindings/aesio/aes.c
756768
#: shared-bindings/busio/SPI.c shared-bindings/microcontroller/Pin.c
757769
#: shared-bindings/neopixel_write/__init__.c
758770
#: shared-bindings/terminalio/Terminal.c
@@ -845,6 +857,10 @@ msgstr ""
845857
msgid "File exists"
846858
msgstr ""
847859

860+
#: ports/atmel-samd/common-hal/canio/Listener.c
861+
msgid "Filters too complex"
862+
msgstr ""
863+
848864
#: ports/cxd56/common-hal/camera/Camera.c
849865
msgid "Format not supported"
850866
msgstr ""
@@ -1127,6 +1143,10 @@ msgstr ""
11271143
msgid "Maximum x value when mirrored is %d"
11281144
msgstr ""
11291145

1146+
#: shared-bindings/canio/Message.c
1147+
msgid "Messages limited to 8 bytes"
1148+
msgstr ""
1149+
11301150
#: supervisor/shared/safe_mode.c
11311151
msgid "MicroPython NLR jump failed. Likely memory corruption."
11321152
msgstr ""
@@ -2310,6 +2330,10 @@ msgstr ""
23102330
msgid "exceptions must derive from BaseException"
23112331
msgstr ""
23122332

2333+
#: shared-bindings/canio/CAN.c shared-bindings/canio/Listener.c
2334+
msgid "expected '%q' but got '%q'"
2335+
msgstr ""
2336+
23132337
#: py/objstr.c
23142338
msgid "expected ':' after format specifier"
23152339
msgstr ""
@@ -3147,6 +3171,10 @@ msgstr ""
31473171
msgid "source palette too large"
31483172
msgstr ""
31493173

3174+
#: shared-bindings/canio/Message.c
3175+
msgid "specify size or data, but not both"
3176+
msgstr ""
3177+
31503178
#: py/objstr.c
31513179
msgid "start/end indices"
31523180
msgstr ""
@@ -3261,7 +3289,7 @@ msgid "tuple/list has wrong length"
32613289
msgstr ""
32623290

32633291
#: ports/atmel-samd/common-hal/busio/UART.c ports/nrf/common-hal/busio/UART.c
3264-
#: shared-bindings/busio/UART.c
3292+
#: shared-bindings/busio/UART.c shared-bindings/canio/CAN.c
32653293
msgid "tx and rx cannot both be None"
32663294
msgstr ""
32673295

‎main.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,10 @@
8181
#include "supervisor/shared/bluetooth.h"
8282
#endif
8383

84+
#if CIRCUITPY_CANIO
85+
#include "common-hal/canio/CAN.h"
86+
#endif
87+
8488
void do_str(const char *src, mp_parse_input_kind_t input_kind) {
8589
mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0);
8690
if (lex == NULL) {
@@ -226,6 +230,10 @@ void cleanup_after_vm(supervisor_allocation* heap) {
226230
free_memory(heap);
227231
supervisor_move_memory();
228232

233+
#if CIRCUITPY_CANIO
234+
common_hal_canio_reset();
235+
#endif
236+
229237
reset_port();
230238
#if CIRCUITPY_BOARD
231239
reset_board_busses();

‎ports/atmel-samd/Makefile

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,10 @@ SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
393393
$(HEADER_BUILD)/sdiodata.h: tools/mksdiodata.py | $(HEADER_BUILD)
394394
$(Q)$(PYTHON3) $< > $@
395395

396+
SRC_QSTR += $(HEADER_BUILD)/candata.h
397+
$(HEADER_BUILD)/candata.h: tools/mkcandata.py | $(HEADER_BUILD)
398+
$(Q)$(PYTHON3) $< > $@
399+
396400
SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
397401
# Sources that only hold QSTRs after pre-processing.
398402
SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c

‎ports/atmel-samd/asf4_conf/same51/peripheral_clk_config.h

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1165,6 +1165,88 @@
11651165
#define CONF_SDHC1_SLOW_FREQUENCY 12000000
11661166
#endif
11671167

1168+
// <h> CAN Clock Settings
1169+
// <y> CAN Clock source
1170+
1171+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1172+
1173+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1174+
1175+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1176+
1177+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1178+
1179+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1180+
1181+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1182+
1183+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1184+
1185+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1186+
1187+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1188+
1189+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1190+
1191+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1192+
1193+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1194+
1195+
// <i> Select the clock source for CAN.
1196+
// <id> sdhc_gclk_selection
1197+
#ifndef CONF_GCLK_CAN0_SRC
1198+
#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
1199+
#endif
1200+
1201+
/**
1202+
* \def CAN FREQUENCY
1203+
* \brief CAN's Clock frequency
1204+
*/
1205+
#ifndef CONF_CAN0_FREQUENCY
1206+
#define CONF_CAN0_FREQUENCY 120000000
1207+
#endif
1208+
1209+
// <h> CAN Clock Settings
1210+
// <y> CAN Clock source
1211+
1212+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1213+
1214+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1215+
1216+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1217+
1218+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1219+
1220+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1221+
1222+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1223+
1224+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1225+
1226+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1227+
1228+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1229+
1230+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1231+
1232+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1233+
1234+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1235+
1236+
// <i> Select the clock source for CAN.
1237+
// <id> sdhc_gclk_selection
1238+
#ifndef CONF_GCLK_CAN1_SRC
1239+
#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
1240+
#endif
1241+
1242+
/**
1243+
* \def CAN FREQUENCY
1244+
* \brief CAN's Clock frequency
1245+
*/
1246+
#ifndef CONF_CAN1_FREQUENCY
1247+
#define CONF_CAN1_FREQUENCY 120000000
1248+
#endif
1249+
11681250
// <<< end of configuration section >>>
11691251

11701252
#endif // PERIPHERAL_CLK_CONFIG_H

‎ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1165,6 +1165,88 @@
11651165
#define CONF_SDHC1_SLOW_FREQUENCY 12000000
11661166
#endif
11671167

1168+
// <h> CAN Clock Settings
1169+
// <y> CAN Clock source
1170+
1171+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1172+
1173+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1174+
1175+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1176+
1177+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1178+
1179+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1180+
1181+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1182+
1183+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1184+
1185+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1186+
1187+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1188+
1189+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1190+
1191+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1192+
1193+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1194+
1195+
// <i> Select the clock source for CAN.
1196+
// <id> sdhc_gclk_selection
1197+
#ifndef CONF_GCLK_CAN0_SRC
1198+
#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
1199+
#endif
1200+
1201+
/**
1202+
* \def CAN FREQUENCY
1203+
* \brief CAN's Clock frequency
1204+
*/
1205+
#ifndef CONF_CAN0_FREQUENCY
1206+
#define CONF_CAN0_FREQUENCY 120000000
1207+
#endif
1208+
1209+
// <h> CAN Clock Settings
1210+
// <y> CAN Clock source
1211+
1212+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1213+
1214+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1215+
1216+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1217+
1218+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1219+
1220+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1221+
1222+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1223+
1224+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1225+
1226+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1227+
1228+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1229+
1230+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1231+
1232+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1233+
1234+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1235+
1236+
// <i> Select the clock source for CAN.
1237+
// <id> sdhc_gclk_selection
1238+
#ifndef CONF_GCLK_CAN1_SRC
1239+
#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
1240+
#endif
1241+
1242+
/**
1243+
* \def CAN FREQUENCY
1244+
* \brief CAN's Clock frequency
1245+
*/
1246+
#ifndef CONF_CAN1_FREQUENCY
1247+
#define CONF_CAN1_FREQUENCY 120000000
1248+
#endif
1249+
11681250
// <<< end of configuration section >>>
11691251

11701252
#endif // PERIPHERAL_CLK_CONFIG_H

‎ports/atmel-samd/boards/common.template.ld

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,15 @@ SECTIONS
4343
_sidata = .; /* start of .data section */
4444
} >FLASH_FIRMWARE
4545

46+
/* Data accessed by the CAN peripheral must be in the first 64kB RAM */
47+
/* place it at the very start of RAM, before the .data section */
48+
/* it is zeroed by reset_port */
49+
.canram (NOLOAD) :
50+
{
51+
. = ALIGN(4);
52+
*(.canram)
53+
} > RAM
54+
4655
/* This is the initialized data section
4756
The program executes knowing that the data is in the RAM
4857
but the loader puts the initial values in the FLASH_FIRMWARE (inidata).
@@ -61,7 +70,7 @@ SECTIONS
6170
} >RAM
6271

6372
/* Uninitialized data section */
64-
.bss :
73+
.bss (NOLOAD) :
6574
{
6675
. = ALIGN(4);
6776
_sbss = .;

‎ports/atmel-samd/boards/feather_m4_can/mpconfigboard.mk

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,4 @@ EXTERNAL_FLASH_DEVICES = GD25Q16C
1212
LONGINT_IMPL = MPZ
1313

1414
CIRCUITPY_VECTORIO = 1
15+
CIRCUITPY_CANIO = 1

‎ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,4 @@ EXTERNAL_FLASH_DEVICES = "N25Q256A"
1212
LONGINT_IMPL = MPZ
1313

1414
CIRCUITPY_SDIOIO = 1
15+
CIRCUITPY_CANIO = 1

‎ports/atmel-samd/boards/same54_xplained/pins.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,9 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
4848

4949
{ MP_OBJ_NEW_QSTR(MP_QSTR_QT), MP_ROM_PTR(&pin_PA16) },
5050

51-
{ MP_OBJ_NEW_QSTR(MP_QSTR_CANRX), MP_ROM_PTR(&pin_PB12) },
52-
{ MP_OBJ_NEW_QSTR(MP_QSTR_CANTX), MP_ROM_PTR(&pin_PB13) },
51+
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB13) },
52+
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB12) },
53+
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_STANDBY), MP_ROM_PTR(&pin_PC13) },
5354

5455
// EXT1 header
5556
{ MP_OBJ_NEW_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },

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