Merge remote-tracking branch 'origin/main' into main

weblate · weblate · commit affc9da56c8b · 2021-05-08T15:47:32.000+02:00
diff --git a/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h
@@ -1,4 +1,4 @@
-// Circuit Python SAMD21 clock tree:
+// CircuitPython SAMD21 clock tree:
 // DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK0, GCLK1
 //   GCLK0 (48MHz) -> peripherals
 //   GLCK1 (48MHz divided by 150 = 320Khz) -> DAC peripheral (DAC requires 350KHz or lower)
diff --git a/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h
@@ -1,4 +1,4 @@
-// Circuit Python SAMD51 clock tree:
+// CircuitPython SAMD51 clock tree:
 // DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6
 //   GCLK1 (48MHz) -> 48 MHz peripherals
 //   GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0
diff --git a/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same51/hpl_gclk_config.h
@@ -1,4 +1,4 @@
-// Circuit Python SAMD51 clock tree:
+// CircuitPython SAMD51 clock tree:
 // DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6
 //   GCLK1 (48MHz) -> 48 MHz peripherals
 //   GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0
diff --git a/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h b/ports/atmel-samd/asf4_conf/same54/hpl_gclk_config.h
@@ -1,4 +1,4 @@
-// Circuit Python SAMD51 clock tree:
+// CircuitPython SAMD51 clock tree:
 // DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6
 //   GCLK1 (48MHz) -> 48 MHz peripherals
 //   GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0
diff --git a/ports/nrf/boards/common.template.ld b/ports/nrf/boards/common.template.ld
@@ -136,7 +136,7 @@ SECTIONS
         . = ALIGN(4);
     } >APP_RAM
 
-    /* Remove exception unwinding information, since Circuit Python
+    /* Remove exception unwinding information, since CircuitPython
        does not support this GCC feature. */
     /DISCARD/ :
     {
diff --git a/ports/nrf/common-hal/rtc/RTC.c b/ports/nrf/common-hal/rtc/RTC.c
@@ -42,7 +42,7 @@ __attribute__((section(".uninitialized"))) static uint32_t rtc_offset[3];
 // the system crashes or reboots, these values will remain undisturbed and the
 // RTC offset will remain valid.
 //
-// If Circuit Python is updated or these symbols shift around, the prefix and
+// If CircuitPython is updated or these symbols shift around, the prefix and
 // suffix will no longer match, and the time will no longer be valid.
 #define RTC_OFFSET_CHECK_PREFIX 0x25ea7e2a
 #define RTC_OFFSET_CHECK_SUFFIX 0x2b80b69e
diff --git a/ports/nrf/supervisor/port.c b/ports/nrf/supervisor/port.c
@@ -282,7 +282,7 @@ void reset_cpu(void) {
 }
 
 // The uninitialized data section is placed directly after BSS, under the theory
-// that Circuit Python has a lot more .data and .bss than the bootloader.  As a
+// that CircuitPython has a lot more .data and .bss than the bootloader.  As a
 // result, this section is less likely to be tampered with by the bootloader.
 extern uint32_t _euninitialized;
 
diff --git a/shared-bindings/_pixelbuf/PixelBuf.c b/shared-bindings/_pixelbuf/PixelBuf.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-bindings/_pixelbuf/PixelBuf.h b/shared-bindings/_pixelbuf/PixelBuf.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-bindings/_pixelbuf/__init__.c b/shared-bindings/_pixelbuf/__init__.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-bindings/_pixelbuf/__init__.h b/shared-bindings/_pixelbuf/__init__.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-bindings/aesio/aes.c b/shared-bindings/aesio/aes.c
@@ -28,7 +28,7 @@
 //|              from binascii import hexlify
 //|
 //|              key = b'Sixteen byte key'
-//|              inp = b'Circuit Python!!' # Note: 16-bytes long
+//|              inp = b'CircuitPython!!!' # Note: 16-bytes long
 //|              outp = bytearray(len(inp))
 //|              cipher = aesio.AES(key, aesio.mode.MODE_ECB)
 //|              cipher.encrypt_into(inp, outp)
diff --git a/shared-bindings/bitops/__init__.c b/shared-bindings/bitops/__init__.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-bindings/bitops/__init__.h b/shared-bindings/bitops/__init__.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-module/_pixelbuf/PixelBuf.c b/shared-module/_pixelbuf/PixelBuf.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-module/_pixelbuf/PixelBuf.h b/shared-module/_pixelbuf/PixelBuf.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-module/bitops/__init__.c b/shared-module/bitops/__init__.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/shared-module/bitops/__init__.h b/shared-module/bitops/__init__.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython
+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython
  *
  * The MIT License (MIT)
  *
diff --git a/tools/cpboard.py b/tools/cpboard.py
@@ -630,7 +630,7 @@ def print_error_exit(args, e):
 def main():
     import argparse
 
-    cmd_parser = argparse.ArgumentParser(description="Circuit Python Board Tool")
+    cmd_parser = argparse.ArgumentParser(description="CircuitPython Board Tool")
     cmd_parser.add_argument("board", help="build_name, vid:pid or /dev/tty")
     cmd_parser.add_argument("-f", "--firmware", help="upload UF2 firmware file")
     cmd_parser.add_argument("-c", "--command", help="program passed in as string")

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// Circuit Python SAMD21 clock tree:`
	`1`	`+// CircuitPython SAMD21 clock tree:`
`2`	`2`	`// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK0, GCLK1`
`3`	`3`	`// GCLK0 (48MHz) -> peripherals`
`4`	`4`	`// GLCK1 (48MHz divided by 150 = 320Khz) -> DAC peripheral (DAC requires 350KHz or lower)`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-// Circuit Python SAMD51 clock tree:`
	`1`	`+// CircuitPython SAMD51 clock tree:`
`2`	`2`	`// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5, GCLK6`
`3`	`3`	`// GCLK1 (48MHz) -> 48 MHz peripherals`
`4`	`4`	`// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0`
Original file line number	Diff line number	Diff line change
`@@ -136,7 +136,7 @@ SECTIONS`
`136`	`136`	`. = ALIGN(4);`
`137`	`137`	`} >APP_RAM`
`138`	`138`
`139`		`- /* Remove exception unwinding information, since Circuit Python`
	`139`	`+ /* Remove exception unwinding information, since CircuitPython`
`140`	`140`	`does not support this GCC feature. */`
`141`	`141`	`/DISCARD/ :`
`142`	`142`	`{`
Original file line number	Diff line number	Diff line change
`@@ -282,7 +282,7 @@ void reset_cpu(void) {`
`282`	`282`	`}`
`283`	`283`
`284`	`284`	`// The uninitialized data section is placed directly after BSS, under the theory`
`285`		`-// that Circuit Python has a lot more .data and .bss than the bootloader. As a`
	`285`	`+// that CircuitPython has a lot more .data and .bss than the bootloader. As a`
`286`	`286`	`// result, this section is less likely to be tampered with by the bootloader.`
`287`	`287`	`extern uint32_t _euninitialized;`
`288`	`288`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`/*`
`2`		`- * This file is part of the Circuit Python project, https://github.com/adafruit/circuitpython`
	`2`	`+ * This file is part of the CircuitPython project, https://github.com/adafruit/circuitpython`
`3`	`3`	`*`
`4`	`4`	`* The MIT License (MIT)`
`5`	`5`	`*`