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10 | 10 | #define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
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11 | 11 | #endif
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12 | 12 |
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| 13 | +// NOTE: THIS WORKAROUND CAUSES BLE CODE TO CRASH; tested on 2019-03-11. |
13 | 14 | // Turn on nrfx supported workarounds for errata in Rev1 of nRF52840
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14 | 15 | #ifdef NRF52840_XXAA
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15 |
| - #define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 1 |
| 16 | +// #define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 1 |
16 | 17 | #endif
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17 | 18 |
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18 | 19 | // SPI
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25 | 26 | // We could write an interrupt handler that checks whether it's
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26 | 27 | // being used for SPI or I2C, but perhaps two I2C's and 1-2 SPI's are good enough for now.
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27 | 28 |
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28 |
| -// Enable SPIM2 and SPIM3 (if available) |
| 29 | +// Enable SPIM1, SPIM2 and SPIM3 (if available) |
| 30 | +// No conflict with TWIM0. |
| 31 | +#define NRFX_SPIM1_ENABLED 1 |
29 | 32 | #define NRFX_SPIM2_ENABLED 1
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30 |
| -#ifdef NRF_SPIM3 |
31 |
| - #define NRFX_SPIM3_ENABLED 1 |
32 |
| -#else |
33 |
| - #define NRFX_SPIM3_ENABLED 0 |
34 |
| -#endif |
| 33 | +// DON'T ENABLE SPIM3 DUE TO ANOMALY WORKAROUND FAILURE (SEE ABOVE). |
| 34 | +// #ifdef NRF52840_XXAA |
| 35 | +// #define NRFX_SPIM_EXTENDED_ENABLED 1 |
| 36 | +// #define NRFX_SPIM3_ENABLED 1 |
| 37 | +// #else |
| 38 | +// #define NRFX_SPIM3_ENABLED 0 |
| 39 | +// #endif |
35 | 40 |
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36 | 41 |
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37 | 42 | #define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
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40 | 45 | // QSPI
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41 | 46 | #define NRFX_QSPI_ENABLED 1
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42 | 47 |
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43 |
| -// TWI aka. I2C; enable TWIM0 and TWIM1 (no conflict with SPIM choices) |
| 48 | +// TWI aka. I2C; enable a single bus: TWIM0 (no conflict with SPIM1 and SPIM2) |
44 | 49 | #define NRFX_TWIM_ENABLED 1
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45 | 50 | #define NRFX_TWIM0_ENABLED 1
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46 |
| -#define NRFX_TWIM1_ENABLED 1 |
| 51 | +//#define NRFX_TWIM1_ENABLED 1 |
47 | 52 |
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48 | 53 | #define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
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49 | 54 | #define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY NRF_TWIM_FREQ_400K
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