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robert-hh
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mimxrt/boards: Add the Seeed ARCH MIX board.
The ARCH MIX board exposes the Ethernet Pins at it's connectors. Therefore the software is configured for using a LAN8720 PHY device. Breakout boards with the LAN8720 are easily available.
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‎ports/mimxrt/boards/SEEED_ARCH_MIX/SEEED_ARCH_MIX_flexspi_nor_config.h

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/*
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* Copyright 2019 NXP.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1020_flexspi_nor_config.h
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#ifndef __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__
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#define __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__
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#include <stdint.h>
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#include <stdbool.h>
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#include "fsl_common.h"
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/*! @name Driver version */
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/*@{*/
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/*! @brief XIP_BOARD driver version 2.0.0. */
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#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* FLEXSPI memory config block related defintions */
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI Feature related definitions */
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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/* Lookup table related defintions */
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// !@brief Definitions for FlexSPI Serial Clock Frequency
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typedef enum _FlexSpiSerialClockFreq
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{
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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kFlexSpiSerialClk_166MHz = 8,
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kFlexSpiSerialClk_200MHz = 9,
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} flexspi_serial_clk_freq_t;
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// !@brief FlexSPI clock configuration type
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enum
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{
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kFlexSpiClk_SDR, // !< Clock configure for SDR mode
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kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
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};
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// !@brief FlexSPI Read Sample Clock Source definition
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typedef enum _FlashReadSampleClkSource
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{
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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} flexspi_read_sample_clk_t;
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// !@brief Misc feature bit definitions
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enum
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{
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kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
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kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
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kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
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kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
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kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
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};
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// !@brief Flash Type Definition
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enum
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{
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kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
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kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
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kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
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};
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// !@brief Flash Pad Definitions
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enum
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{
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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};
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// !@brief FlexSPI LUT Sequence structure
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typedef struct _lut_sequence
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{
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uint8_t seqNum; // !< Sequence Number, valid number: 1-16
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uint8_t seqId; // !< Sequence Index, valid number: 0-15
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uint16_t reserved;
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} flexspi_lut_seq_t;
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// !@brief Flash Configuration Command Type
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enum
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{
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kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
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kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
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kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
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kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
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kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
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kDeviceConfigCmdType_Reset, // !< Reset device command
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};
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// !@brief FlexSPI Memory Configuration Block
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typedef struct _FlexSPIConfig
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{
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uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
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uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
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uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
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uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
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uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
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uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
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uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
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// ! Serial NAND, need to refer to datasheet
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uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
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uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
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// ! Generic configuration, etc.
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uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
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// ! DPI/QPI/OPI switch or reset command
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flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
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// ! sequence number, [31:16] Reserved
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uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
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uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
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uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
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flexspi_lut_seq_t
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configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
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uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
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uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
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uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
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uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
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// ! details
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uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
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uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
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uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
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// ! Chapter for more details
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uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
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// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
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uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
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uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
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uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
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uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
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uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
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uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
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uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
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uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
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uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
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uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
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uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
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uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
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uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
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uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
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// ! busy flag is 0 when flash device is busy
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uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
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flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
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uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
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} flexspi_mem_config_t;
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/* */
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
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/*
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* Serial NOR configuration block
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*/
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typedef struct _flexspi_nor_config
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{
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flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
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uint32_t pageSize; // !< Page size of Serial NOR
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uint32_t sectorSize; // !< Sector size of Serial NOR
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uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
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uint8_t isUniformBlockSize; // !< Sector/Block size is the same
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uint8_t reserved0[2]; // !< Reserved for future use
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uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
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uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
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uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
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uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
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uint32_t blockSize; // !< Block size
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uint32_t reserve2[11]; // !< Reserved for future use
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} flexspi_nor_config_t;
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#define FLASH_BUSY_STATUS_POL 0
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#define FLASH_BUSY_STATUS_OFFSET 0
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SEEED_ARCH_MIX_FLEXSPI_NOR_CONFIG__ */

‎ports/mimxrt/boards/SEEED_ARCH_MIX/board.json

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{
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"deploy": [
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"deploy.md"
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],
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"docs": "",
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"features": [
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"MicroSD",
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"MicroUSB",
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"SDRAM",
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"RGB LED"
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],
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"images": [
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"main1.jpg"
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],
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"mcu": "mimxrt",
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"product": "Arch Mix",
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"thumbnail": "",
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"url": "https://wiki.seeedstudio.com/Arch_Mix/",
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"vendor": "Seeed Technology Co.,Ltd."
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}

‎ports/mimxrt/boards/SEEED_ARCH_MIX/clock_config.h

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/*
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* Copyright 2017-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes default configuration of clocks.
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*
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*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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/* Clock outputs (values are in Hz): */
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#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
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#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
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#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
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#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
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#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
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#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
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#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
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#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
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#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
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#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
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#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
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#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
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#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
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#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
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#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
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#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
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#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
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#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
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#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
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#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
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#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
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#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
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#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
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#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
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/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
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/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
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/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
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*/
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extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
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/*******************************************************************************
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* API for BOARD_BootClockRUN configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockRUN(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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#endif /* _CLOCK_CONFIG_H_ */

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