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| 1 | +#include "py/objtuple.h" |
| 2 | +#include "shared-bindings/board/__init__.h" |
| 3 | + |
| 4 | +STATIC const mp_rom_obj_tuple_t tft_r_pins = { |
| 5 | + {&mp_type_tuple}, |
| 6 | + 5, |
| 7 | + { |
| 8 | + MP_ROM_PTR(&pin_GPIO14), |
| 9 | + MP_ROM_PTR(&pin_GPIO15), |
| 10 | + MP_ROM_PTR(&pin_GPIO16), |
| 11 | + MP_ROM_PTR(&pin_GPIO17), |
| 12 | + MP_ROM_PTR(&pin_GPIO18), |
| 13 | + } |
| 14 | +}; |
| 15 | + |
| 16 | +STATIC const mp_rom_obj_tuple_t tft_g_pins = { |
| 17 | + {&mp_type_tuple}, |
| 18 | + 6, |
| 19 | + { |
| 20 | + MP_ROM_PTR(&pin_GPIO8), |
| 21 | + MP_ROM_PTR(&pin_GPIO9), |
| 22 | + MP_ROM_PTR(&pin_GPIO10), |
| 23 | + MP_ROM_PTR(&pin_GPIO11), |
| 24 | + MP_ROM_PTR(&pin_GPIO12), |
| 25 | + MP_ROM_PTR(&pin_GPIO13), |
| 26 | + } |
| 27 | +}; |
| 28 | + |
| 29 | +STATIC const mp_rom_obj_tuple_t tft_b_pins = { |
| 30 | + {&mp_type_tuple}, |
| 31 | + 5, |
| 32 | + { |
| 33 | + MP_ROM_PTR(&pin_GPIO3), |
| 34 | + MP_ROM_PTR(&pin_GPIO4), |
| 35 | + MP_ROM_PTR(&pin_GPIO5), |
| 36 | + MP_ROM_PTR(&pin_GPIO6), |
| 37 | + MP_ROM_PTR(&pin_GPIO7), |
| 38 | + } |
| 39 | +}; |
| 40 | + |
| 41 | +STATIC const mp_rom_map_elem_t tft_table[] = { |
| 42 | + { MP_ROM_QSTR(MP_QSTR_de), MP_ROM_PTR(&pin_GPIO45) }, |
| 43 | + { MP_ROM_QSTR(MP_QSTR_vsync), MP_ROM_PTR(&pin_GPIO48) }, |
| 44 | + { MP_ROM_QSTR(MP_QSTR_hsync), MP_ROM_PTR(&pin_GPIO47) }, |
| 45 | + { MP_ROM_QSTR(MP_QSTR_dclk), MP_ROM_PTR(&pin_GPIO21) }, |
| 46 | + { MP_ROM_QSTR(MP_QSTR_red), MP_ROM_PTR(&tft_r_pins) }, |
| 47 | + { MP_ROM_QSTR(MP_QSTR_green), MP_ROM_PTR(&tft_g_pins) }, |
| 48 | + { MP_ROM_QSTR(MP_QSTR_blue), MP_ROM_PTR(&tft_b_pins) }, |
| 49 | +}; |
| 50 | +MP_DEFINE_CONST_DICT(tft_dict, tft_table); |
| 51 | + |
| 52 | +STATIC const mp_rom_map_elem_t timings800_table[] = { |
| 53 | + { MP_ROM_QSTR(MP_QSTR_frequency), MP_ROM_INT(6500000) }, // nominal 16MHz, but display is unstable/tears at that frequency |
| 54 | + { MP_ROM_QSTR(MP_QSTR_width), MP_ROM_INT(800) }, |
| 55 | + { MP_ROM_QSTR(MP_QSTR_height), MP_ROM_INT(480) }, |
| 56 | + { MP_ROM_QSTR(MP_QSTR_hsync_pulse_width), MP_ROM_INT(30) }, |
| 57 | + { MP_ROM_QSTR(MP_QSTR_hsync_front_porch), MP_ROM_INT(210) }, |
| 58 | + { MP_ROM_QSTR(MP_QSTR_hsync_back_porch), MP_ROM_INT(16) }, |
| 59 | + { MP_ROM_QSTR(MP_QSTR_hsync_idle_low), MP_ROM_FALSE }, |
| 60 | + { MP_ROM_QSTR(MP_QSTR_vsync_pulse_width), MP_ROM_INT(13) }, |
| 61 | + { MP_ROM_QSTR(MP_QSTR_vsync_front_porch), MP_ROM_INT(22) }, |
| 62 | + { MP_ROM_QSTR(MP_QSTR_vsync_back_porch), MP_ROM_INT(10) }, |
| 63 | + { MP_ROM_QSTR(MP_QSTR_vsync_idle_low), MP_ROM_FALSE }, |
| 64 | + { MP_ROM_QSTR(MP_QSTR_de_idle_high), MP_ROM_FALSE }, |
| 65 | + { MP_ROM_QSTR(MP_QSTR_pclk_active_high), MP_ROM_FALSE }, |
| 66 | + { MP_ROM_QSTR(MP_QSTR_pclk_idle_high), MP_ROM_FALSE }, |
| 67 | +}; |
| 68 | +MP_DEFINE_CONST_DICT(timings800_dict, timings800_table); |
| 69 | + |
| 70 | + |
| 71 | +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { |
| 72 | + CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS |
| 73 | + |
| 74 | + { MP_ROM_QSTR(MP_QSTR_TFT), MP_ROM_PTR(&tft_dict) }, |
| 75 | + { MP_ROM_QSTR(MP_QSTR_TIMINGS800), MP_ROM_PTR(&timings800_dict) }, |
| 76 | + { MP_ROM_QSTR(MP_QSTR_BACKLIGHT), MP_ROM_PTR(&pin_GPIO39) }, |
| 77 | + |
| 78 | + { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) }, |
| 79 | + { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) }, |
| 80 | + { MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_GPIO2) }, |
| 81 | + { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) }, |
| 82 | + { MP_ROM_QSTR(MP_QSTR_TFTB1), MP_ROM_PTR(&pin_GPIO3) }, |
| 83 | + { MP_ROM_QSTR(MP_QSTR_TFTB2), MP_ROM_PTR(&pin_GPIO4) }, |
| 84 | + { MP_ROM_QSTR(MP_QSTR_TFTB3), MP_ROM_PTR(&pin_GPIO5) }, |
| 85 | + { MP_ROM_QSTR(MP_QSTR_TFTB4), MP_ROM_PTR(&pin_GPIO6) }, |
| 86 | + { MP_ROM_QSTR(MP_QSTR_TFTB5), MP_ROM_PTR(&pin_GPIO7) }, |
| 87 | + { MP_ROM_QSTR(MP_QSTR_TFTG1), MP_ROM_PTR(&pin_GPIO8) }, |
| 88 | + { MP_ROM_QSTR(MP_QSTR_TFTG2), MP_ROM_PTR(&pin_GPIO9) }, |
| 89 | + { MP_ROM_QSTR(MP_QSTR_TFTG3), MP_ROM_PTR(&pin_GPIO10) }, |
| 90 | + { MP_ROM_QSTR(MP_QSTR_TFTG4), MP_ROM_PTR(&pin_GPIO11) }, |
| 91 | + { MP_ROM_QSTR(MP_QSTR_TFTG5), MP_ROM_PTR(&pin_GPIO12) }, |
| 92 | + { MP_ROM_QSTR(MP_QSTR_TFTG6), MP_ROM_PTR(&pin_GPIO13) }, |
| 93 | + { MP_ROM_QSTR(MP_QSTR_TFTR1), MP_ROM_PTR(&pin_GPIO14) }, |
| 94 | + { MP_ROM_QSTR(MP_QSTR_TFTR2), MP_ROM_PTR(&pin_GPIO15) }, |
| 95 | + { MP_ROM_QSTR(MP_QSTR_TFTR3), MP_ROM_PTR(&pin_GPIO16) }, |
| 96 | + { MP_ROM_QSTR(MP_QSTR_TFTR4), MP_ROM_PTR(&pin_GPIO17) }, |
| 97 | + { MP_ROM_QSTR(MP_QSTR_TFTR5), MP_ROM_PTR(&pin_GPIO18) }, |
| 98 | + { MP_ROM_QSTR(MP_QSTR_IO19), MP_ROM_PTR(&pin_GPIO19) }, |
| 99 | + { MP_ROM_QSTR(MP_QSTR_IO20), MP_ROM_PTR(&pin_GPIO20) }, |
| 100 | + { MP_ROM_QSTR(MP_QSTR_dclk), MP_ROM_PTR(&pin_GPIO21) }, |
| 101 | + { MP_ROM_QSTR(MP_QSTR_IO35), MP_ROM_PTR(&pin_GPIO35) }, |
| 102 | + { MP_ROM_QSTR(MP_QSTR_IO36), MP_ROM_PTR(&pin_GPIO36) }, |
| 103 | + { MP_ROM_QSTR(MP_QSTR_IO37), MP_ROM_PTR(&pin_GPIO37) }, |
| 104 | + { MP_ROM_QSTR(MP_QSTR_IO38), MP_ROM_PTR(&pin_GPIO38) }, |
| 105 | + { MP_ROM_QSTR(MP_QSTR_IO39), MP_ROM_PTR(&pin_GPIO39) }, |
| 106 | + { MP_ROM_QSTR(MP_QSTR_IO40), MP_ROM_PTR(&pin_GPIO40) }, |
| 107 | + { MP_ROM_QSTR(MP_QSTR_IO41), MP_ROM_PTR(&pin_GPIO41) }, |
| 108 | + { MP_ROM_QSTR(MP_QSTR_IO42), MP_ROM_PTR(&pin_GPIO42) }, |
| 109 | + { MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) }, |
| 110 | + { MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) }, |
| 111 | + { MP_ROM_QSTR(MP_QSTR_de), MP_ROM_PTR(&pin_GPIO45) }, |
| 112 | + { MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46) }, |
| 113 | + { MP_ROM_QSTR(MP_QSTR_hsync), MP_ROM_PTR(&pin_GPIO47) }, |
| 114 | + { MP_ROM_QSTR(MP_QSTR_vsync), MP_ROM_PTR(&pin_GPIO48) }, |
| 115 | + { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO48) }, |
| 116 | + |
| 117 | + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) }, |
| 118 | + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) }, |
| 119 | + |
| 120 | + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, |
| 121 | +}; |
| 122 | +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); |
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