soc: placeholder for esp32s3 HAL driver

soc rtc

Author: suda-morris

components/esp_serial_slave_link/essl_sdio.c

@@ -14,12 +14,17 @@
 
 #include "essl_sdio.h"
 #include "esp_log.h"
-#include "soc/host_reg.h"
 #include "freertos/task.h"
 #include "essl_internal.h"
+#include "soc/soc_caps.h"
+
+#if SOC_SDIO_SLAVE_SUPPORTED
+#include "soc/host_reg.h"
 
 static const char TAG[] = "essl_sdio";
 
+#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
+
 #define ESSL_CMD53_END_ADDR    0x1f800
 
 #define TX_BUFFER_MAX   0x1000
@@ -452,4 +457,6 @@ void essl_sdio_reset_cnt(void *arg)
     essl_sdio_context_t* ctx = arg;
     ctx->rx_got_bytes = 0;
     ctx->tx_sent_buffers = 0;
-}
+}
+
+#endif // #if SOC_SDIO_SLAVE_SUPPORTED

components/soc/include/hal/adc_types.h

@@ -1,8 +1,22 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
 #pragma once
 
-#include "soc/adc_caps.h"
-#include "sdkconfig.h"
 #include <stdbool.h>
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/adc_caps.h"
 
 /**
  * @brief ADC units selected handle.
@@ -69,7 +83,7 @@ typedef enum {
     ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */
     ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */
     ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */
-#ifdef CONFIG_IDF_TARGET_ESP32S2
+#if !CONFIG_IDF_TARGET_ESP32
     ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */
 #endif
     ADC_WIDTH_MAX,
@@ -112,7 +126,7 @@ typedef struct {
     };
 } adc_digi_output_data_t;
 
-#ifdef CONFIG_IDF_TARGET_ESP32S2
+#if !CONFIG_IDF_TARGET_ESP32
 
 /**
  * @brief ADC digital controller (DMA mode) clock system setting.
@@ -338,4 +352,4 @@ typedef struct {
     uint32_t threshold;             /*!<Set monitor threshold of adc digital controller. */
 } adc_digi_monitor_t;
 
-#endif // CONFIG_IDF_TARGET_ESP32S2
+#endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3

components/soc/include/hal/spi_types.h

@@ -49,7 +49,7 @@ FLAG_ATTR(spi_event_t)
 #define SPI_HOST    SPI1_HOST
 #define HSPI_HOST   SPI2_HOST
 #define VSPI_HOST   SPI3_HOST
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 // SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2
 #define SPI_HOST    SPI1_HOST
 #define FSPI_HOST   SPI2_HOST

components/soc/include/hal/systimer_hal.h

@@ -71,6 +71,11 @@ void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_
  */
 void systimer_hal_init(void);
 
+/**
+ * @brief  connect alarm unit to selected counter
+ */
+void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id);
+
 #ifdef __cplusplus
 }
 #endif

components/soc/include/hal/touch_sensor_types.h

@@ -129,7 +129,7 @@ typedef enum {
 #define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
 #define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
 
-#elif CONFIG_IDF_TARGET_ESP32S2
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 /**
  * Excessive total time will slow down the touch response.
  * Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
@@ -145,7 +145,7 @@ typedef enum {
                                                     Range: 0 ~ 0xffff */
 #endif // CONFIG_IDF_TARGET_ESP32
 
-#ifdef CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 
 typedef enum {
     TOUCH_PAD_INTR_MASK_DONE = BIT(0),      /*!<Measurement done for one of the enabled channels. */

components/soc/include/soc/lldesc.h

@@ -20,6 +20,8 @@
 #include "esp32/rom/lldesc.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/lldesc.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/lldesc.h"
 #endif
 
 //the size field has 12 bits, but 0 not for 4096.

components/soc/include/soc/soc_memory_layout.h

@@ -211,10 +211,10 @@ inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
 }
 
 inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
-#if !CONFIG_FREERTOS_UNICORE || CONFIG_IDF_TARGET_ESP32S2
-    return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
-#else
+#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
     return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
+#else
+    return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
 #endif
 }
 

components/soc/include/soc_log.h

@@ -36,6 +36,8 @@
 #include "esp32/rom/ets_sys.h"  // will be removed in idf v5.0
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/ets_sys.h"
 #endif
 
 #define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__)

components/soc/soc/esp32/include/soc/host_reg.h

@@ -812,8 +812,6 @@
 #define HOST_SLCHOST_STATE4_V  0xFF
 #define HOST_SLCHOST_STATE4_S  0
 
-#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
-
 #define HOST_SLCHOST_CONF_W0_REG          (DR_REG_SLCHOST_BASE + 0x6C)
 /* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: */