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Addition of support for imxt1010, 1050 and 1060 families
1 parent d388899 commit f0e5341

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6 files changed

+73
-3
lines changed

6 files changed

+73
-3
lines changed

ports/mimxrt10xx/boards/imxrt1020_evk/flash_config.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,11 @@ const flexspi_nor_config_t qspiflash_config = {
4242
{
4343
.tag = FLEXSPI_CFG_BLK_TAG,
4444
.version = FLEXSPI_CFG_BLK_VERSION,
45-
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
45+
#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX
46+
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromInternally,
47+
#else
48+
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
49+
#endif
4650
.csHoldTime = 1u,
4751
.csSetupTime = 2u,
4852
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,26 @@ const mcu_periph_obj_t mcu_uart_tx_list[9] = {
113113
PERIPH_PIN(4, 3, kIOMUXC_LPUART4_TXD_SELECT_INPUT, 1, &pin_GPIO_06),
114114
};
115115

116+
const mcu_periph_obj_t mcu_uart_rts_list[4] = {
117+
PERIPH_PIN(1, 6, 0, 0, &pin_GPIO_07),
118+
119+
PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_07),
120+
121+
PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_13),
122+
123+
PERIPH_PIN(4, 3, 0, 0, &pin_GPIO_AD_13)
124+
};
125+
126+
const mcu_periph_obj_t mcu_uart_cts_list[4] = {
127+
PERIPH_PIN(1, 6, 0, 0, &pin_GPIO_08),
128+
129+
PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_AD_08),
130+
131+
PERIPH_PIN(3, 1, 0, 0, &pin_GPIO_AD_14),
132+
133+
PERIPH_PIN(4, 3, 0, 0, &pin_GPIO_AD_14),
134+
};
135+
116136
const mcu_pwm_obj_t mcu_pwm_list[20] = {
117137
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 2, &pin_GPIO_02),
118138
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 2, &pin_GPIO_SD_02),

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1011/periph.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,8 @@ extern const mcu_periph_obj_t mcu_spi_miso_list[4];
3636

3737
extern const mcu_periph_obj_t mcu_uart_rx_list[9];
3838
extern const mcu_periph_obj_t mcu_uart_tx_list[9];
39+
const mcu_periph_obj_t mcu_uart_rts_list[4];
40+
const mcu_periph_obj_t mcu_uart_cts_list[4];
3941

4042
extern const mcu_pwm_obj_t mcu_pwm_list[20];
4143

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -127,8 +127,8 @@ const mcu_periph_obj_t mcu_uart_rx_list[18] = {
127127
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_26),
128128
PERIPH_PIN(6, 2, kIOMUXC_LPUART6_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_03),
129129

130-
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
131130
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_09),
131+
PERIPH_PIN(7, 2, kIOMUXC_LPUART7_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_32),
132132

133133
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B0_05),
134134
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B1_11),
@@ -163,6 +163,44 @@ const mcu_periph_obj_t mcu_uart_tx_list[18] = {
163163
PERIPH_PIN(8, 2, kIOMUXC_LPUART8_TX_SELECT_INPUT, 2, &pin_GPIO_EMC_38),
164164
};
165165

166+
const mcu_periph_obj_t mcu_uart_rts_list[9] = {
167+
PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_15),
168+
169+
PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_01),
170+
171+
PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_AD_B1_05),
172+
PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_EMC_16),
173+
174+
PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_18),
175+
176+
PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_27),
177+
178+
PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_29),
179+
180+
PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_07),
181+
182+
PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_03),
183+
};
184+
185+
const mcu_periph_obj_t mcu_uart_cts_list[9] = {
186+
PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B0_14),
187+
188+
PERIPH_PIN(2, 2, 0, 0, &pin_GPIO_AD_B1_00),
189+
190+
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 0, &pin_GPIO_EMC_15),
191+
PERIPH_PIN(3, 2, kIOMUXC_LPUART3_CTS_B_SELECT_INPUT, 1, &pin_GPIO_AD_B1_04),
192+
193+
PERIPH_PIN(4, 2, 0, 0, &pin_GPIO_EMC_17),
194+
195+
PERIPH_PIN(5, 2, 0, 0, &pin_GPIO_EMC_28),
196+
197+
PERIPH_PIN(6, 2, 0, 0, &pin_GPIO_EMC_30),
198+
199+
PERIPH_PIN(7, 2, 0, 0, &pin_GPIO_SD_B1_06),
200+
201+
PERIPH_PIN(8, 2, 0, 0, &pin_GPIO_SD_B0_02),
202+
};
203+
166204
const mcu_pwm_obj_t mcu_pwm_list[67] = {
167205
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 1, &pin_GPIO_EMC_23),
168206
PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, 1, &pin_GPIO_SD_B0_00),

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,8 @@ extern const mcu_periph_obj_t mcu_spi_miso_list[8];
3636

3737
extern const mcu_periph_obj_t mcu_uart_rx_list[18];
3838
extern const mcu_periph_obj_t mcu_uart_tx_list[18];
39+
const mcu_periph_obj_t mcu_uart_rts_list[9];
40+
const mcu_periph_obj_t mcu_uart_cts_list[9];
3941

4042
extern const mcu_pwm_obj_t mcu_pwm_list[67];
4143

ports/mimxrt10xx/supervisor/flexspi_nor_flash_ops.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,11 @@ void flexspi_nor_flash_init(FLEXSPI_Type *base)
324324
config.ahbConfig.enableAHBBufferable = true;
325325
config.ahbConfig.enableReadAddressOpt = true;
326326
config.ahbConfig.enableAHBCachable = true;
327-
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; //kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
327+
#ifdef BOARD_USING_SECONDARY_QSPI_PINMUX
328+
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
329+
#else
330+
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
331+
#endif
328332
FLEXSPI_Init(base, &config);
329333

330334
/* Configure flash settings according to serial flash feature. */

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