Skip to content

Commit ade6fa4

Browse files
aemersonaemerson
committed
[AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal.
1 parent 6f10998 commit ade6fa4

File tree

3 files changed

+107
-5
lines changed

3 files changed

+107
-5
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -597,11 +597,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
597597
.minScalarOrElt(0, s8); // Worst case, we need at least s8.
598598

599599
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
600-
.legalIf([=](const LegalityQuery &Query) {
601-
const LLT &VecTy = Query.Types[0];
602-
// TODO: Support s8 and s16
603-
return VecTy == v2s32 || VecTy == v4s32 || VecTy == v2s64;
604-
});
600+
.legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64}));
605601

606602
getActionDefinitionsBuilder(G_BUILD_VECTOR)
607603
.legalFor({{v8s8, s8},

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
3+
4+
---
5+
name: v8s16
6+
body: |
7+
bb.0:
8+
liveins: $q0
9+
; CHECK-LABEL: name: v8s16
10+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
11+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
12+
; CHECK: %val:_(s16) = G_CONSTANT i16 42
13+
; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
14+
; CHECK: $q0 = COPY [[IVEC]](<8 x s16>)
15+
; CHECK: RET_ReallyLR
16+
%0:_(<8 x s16>) = COPY $q0
17+
%1:_(s32) = G_CONSTANT i32 1
18+
%val:_(s16) = G_CONSTANT i16 42
19+
%2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32)
20+
$q0 = COPY %2(<8 x s16>)
21+
RET_ReallyLR
22+
...
23+
---
24+
name: v2s32
25+
body: |
26+
bb.0:
27+
liveins: $q0
28+
; CHECK-LABEL: name: v2s32
29+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
30+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
31+
; CHECK: %val:_(s32) = G_CONSTANT i32 42
32+
; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
33+
; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
34+
; CHECK: RET_ReallyLR
35+
%0:_(<2 x s32>) = COPY $d0
36+
%1:_(s32) = G_CONSTANT i32 1
37+
%val:_(s32) = G_CONSTANT i32 42
38+
%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32)
39+
$d0 = COPY %2(<2 x s32>)
40+
RET_ReallyLR
41+
...
42+
---
43+
name: v4s32
44+
body: |
45+
bb.0:
46+
liveins: $q0
47+
; CHECK-LABEL: name: v4s32
48+
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
49+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
50+
; CHECK: %val:_(s32) = G_CONSTANT i32 42
51+
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
52+
; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
53+
; CHECK: RET_ReallyLR
54+
%0:_(<4 x s32>) = COPY $q0
55+
%1:_(s32) = G_CONSTANT i32 1
56+
%val:_(s32) = G_CONSTANT i32 42
57+
%2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32)
58+
$q0 = COPY %2(<4 x s32>)
59+
RET_ReallyLR
60+
...
61+
---
62+
name: v2s64
63+
body: |
64+
bb.0:
65+
liveins: $q0
66+
; CHECK-LABEL: name: v2s64
67+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
68+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
69+
; CHECK: %val:_(s64) = G_CONSTANT i64 42
70+
; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
71+
; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
72+
; CHECK: RET_ReallyLR
73+
%0:_(<2 x s64>) = COPY $q0
74+
%1:_(s32) = G_CONSTANT i32 1
75+
%val:_(s64) = G_CONSTANT i64 42
76+
%2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32)
77+
$q0 = COPY %2(<2 x s64>)
78+
RET_ReallyLR
79+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,33 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
3+
---
4+
name: v8s16_fpr
5+
alignment: 4
6+
legalized: true
7+
regBankSelected: true
8+
tracksRegLiveness: true
9+
body: |
10+
bb.0:
11+
liveins: $q1, $h0
312
13+
; CHECK-LABEL: name: v8s16_fpr
14+
; CHECK: liveins: $q1, $h0
15+
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
16+
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
17+
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
18+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
19+
; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
20+
; CHECK: $q0 = COPY [[INSvi16lane]]
21+
; CHECK: RET_ReallyLR implicit $q0
22+
%0:fpr(s16) = COPY $h0
23+
%1:fpr(<8 x s16>) = COPY $q1
24+
%3:gpr(s32) = G_CONSTANT i32 1
25+
%2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
26+
$q0 = COPY %2(<8 x s16>)
27+
RET_ReallyLR implicit $q0
28+
29+
...
30+
---
431
name: v4s32_fpr
532
alignment: 4
633
legalized: true

0 commit comments

Comments
 (0)