[ARM] Add scalar add_sat costs. (llvm#100988)

These can usually generate:
 - qadd / qsub for signed i32 scalars
- uqadd16 / qadd16 / uqsub16 / qsub16 with an extend for signed/unsigned
i8/i16
 - Are expanded to an add + cmp + sel otherwise

This can lead to differences in unrolling etc, but should be a better
cost for the instructions.

Author: davemgreen

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

@@ -1888,7 +1888,8 @@ ARMTTIImpl::getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
 InstructionCost
 ARMTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                   TTI::TargetCostKind CostKind) {
-  switch (ICA.getID()) {
+  unsigned Opc = ICA.getID();
+  switch (Opc) {
   case Intrinsic::get_active_lane_mask:
     // Currently we make a somewhat optimistic assumption that
     // active_lane_mask's are always free. In reality it may be freely folded
@@ -1904,17 +1905,38 @@ ARMTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   case Intrinsic::ssub_sat:
   case Intrinsic::uadd_sat:
   case Intrinsic::usub_sat: {
+    bool IsAdd = (Opc == Intrinsic::sadd_sat || Opc == Intrinsic::ssub_sat);
+    bool IsSigned = (Opc == Intrinsic::sadd_sat || Opc == Intrinsic::ssub_sat);
+    Type *RetTy = ICA.getReturnType();
+
+    if (auto *ITy = dyn_cast<IntegerType>(RetTy)) {
+      if (IsSigned && ST->hasDSP() && ITy->getBitWidth() == 32)
+        return 1; // qadd / qsub
+      if (ST->hasDSP() && (ITy->getBitWidth() == 8 || ITy->getBitWidth() == 16))
+        return 2; // uqadd16 / qadd16 / uqsub16 / qsub16 + possible extend.
+      // Otherwise return the cost of expanding the node. Generally an add +
+      // icmp + sel.
+      CmpInst::Predicate Pred = CmpInst::ICMP_SGT;
+      Type *CondTy = RetTy->getWithNewBitWidth(1);
+      return getArithmeticInstrCost(IsAdd ? Instruction::Add : Instruction::Sub,
+                                    RetTy, CostKind) +
+             2 * getCmpSelInstrCost(BinaryOperator::ICmp, RetTy, CondTy, Pred,
+                                    CostKind) +
+             2 * getCmpSelInstrCost(BinaryOperator::Select, RetTy, CondTy, Pred,
+                                    CostKind);
+    }
+
     if (!ST->hasMVEIntegerOps())
       break;
-    Type *VT = ICA.getReturnType();
 
-    std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VT);
+    std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(RetTy);
     if (LT.second == MVT::v4i32 || LT.second == MVT::v8i16 ||
         LT.second == MVT::v16i8) {
       // This is a base cost of 1 for the vqadd, plus 3 extract shifts if we
       // need to extend the type, as it uses shr(qadd(shl, shl)).
       unsigned Instrs =
-          LT.second.getScalarSizeInBits() == VT->getScalarSizeInBits() ? 1 : 4;
+          LT.second.getScalarSizeInBits() == RetTy->getScalarSizeInBits() ? 1
+                                                                          : 4;
       return LT.first * ST->getMVEVectorCostFactor(CostKind) * Instrs;
     }
     break;
@@ -1948,7 +1970,7 @@ ARMTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   case Intrinsic::fptoui_sat: {
     if (ICA.getArgTypes().empty())
       break;
-    bool IsSigned = ICA.getID() == Intrinsic::fptosi_sat;
+    bool IsSigned = Opc == Intrinsic::fptosi_sat;
     auto LT = getTypeLegalizationCost(ICA.getArgTypes()[0]);
     EVT MTy = TLI->getValueType(DL, ICA.getReturnType());
     // Check for the legal types, with the corect subtarget features.