Skip to content

Commit f7e9d81

Browse files
topperctopperc
committed
[X86] Don't set the operation action for i16 SINT_TO_FP to Promote just because SSE1 is enabled.
Instead do custom promotion in the handler so that we can still allow i16 to be used with fp80. And f64 without sse2.
1 parent 787595b commit f7e9d81

File tree

3 files changed

+44
-45
lines changed

3 files changed

+44
-45
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -238,9 +238,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
238238
// Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
239239
// this operation.
240240
setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
241-
// SSE has no i16 to fp conversion, only i32.
242-
setOperationAction(ISD::SINT_TO_FP, MVT::i16, X86ScalarSSEf32 ? Promote
243-
: Custom);
241+
// SSE has no i16 to fp conversion, only i32. We promote in the handler
242+
// to allow f80 to use i16 and f64 to use i16 with sse1 only
243+
setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
244244
// f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
245245
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
246246
// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
@@ -18441,6 +18441,12 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
1844118441
if (SDValue V = LowerI64IntToFP_AVX512DQ(Op, DAG, Subtarget))
1844218442
return V;
1844318443

18444+
// SSE doesn't have an i16 conversion so we need to promote.
18445+
if (SrcVT == MVT::i16 && isScalarFPTypeInSSEReg(VT)) {
18446+
SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Src);
18447+
return DAG.getNode(ISD::SINT_TO_FP, dl, VT, Ext);
18448+
}
18449+
1844418450
SDValue ValueToStore = Op.getOperand(0);
1844518451
if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) &&
1844618452
!Subtarget.is64Bit())

‎llvm/test/CodeGen/X86/fp-arith.ll

Lines changed: 30 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,8 @@ define x86_fp80 @fiadd_fp80_i16(x86_fp80 %a0, i16 %a1) {
2222
; X64-LABEL: fiadd_fp80_i16:
2323
; X64: # %bb.0:
2424
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
25-
; X64-NEXT: movswl %di, %eax
26-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
27-
; X64-NEXT: fiaddl -{{[0-9]+}}(%rsp)
25+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
26+
; X64-NEXT: fiadds -{{[0-9]+}}(%rsp)
2827
; X64-NEXT: retq
2928
%1 = sitofp i16 %a1 to x86_fp80
3029
%2 = fadd x86_fp80 %a0, %1
@@ -48,9 +47,9 @@ define x86_fp80 @fiadd_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
4847
; X64-LABEL: fiadd_fp80_i16_ld:
4948
; X64: # %bb.0:
5049
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
51-
; X64-NEXT: movswl (%rdi), %eax
52-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
53-
; X64-NEXT: fiaddl -{{[0-9]+}}(%rsp)
50+
; X64-NEXT: movzwl (%rdi), %eax
51+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
52+
; X64-NEXT: fiadds -{{[0-9]+}}(%rsp)
5453
; X64-NEXT: retq
5554
%1 = load i16, i16 *%a1
5655
%2 = sitofp i16 %1 to x86_fp80
@@ -129,9 +128,8 @@ define x86_fp80 @fisub_fp80_i16(x86_fp80 %a0, i16 %a1) {
129128
; X64-LABEL: fisub_fp80_i16:
130129
; X64: # %bb.0:
131130
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
132-
; X64-NEXT: movswl %di, %eax
133-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
134-
; X64-NEXT: fisubl -{{[0-9]+}}(%rsp)
131+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
132+
; X64-NEXT: fisubs -{{[0-9]+}}(%rsp)
135133
; X64-NEXT: retq
136134
%1 = sitofp i16 %a1 to x86_fp80
137135
%2 = fsub x86_fp80 %a0, %1
@@ -155,9 +153,9 @@ define x86_fp80 @fisub_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
155153
; X64-LABEL: fisub_fp80_i16_ld:
156154
; X64: # %bb.0:
157155
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
158-
; X64-NEXT: movswl (%rdi), %eax
159-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
160-
; X64-NEXT: fisubl -{{[0-9]+}}(%rsp)
156+
; X64-NEXT: movzwl (%rdi), %eax
157+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
158+
; X64-NEXT: fisubs -{{[0-9]+}}(%rsp)
161159
; X64-NEXT: retq
162160
%1 = load i16, i16 *%a1
163161
%2 = sitofp i16 %1 to x86_fp80
@@ -236,9 +234,8 @@ define x86_fp80 @fisubr_fp80_i16(x86_fp80 %a0, i16 %a1) {
236234
; X64-LABEL: fisubr_fp80_i16:
237235
; X64: # %bb.0:
238236
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
239-
; X64-NEXT: movswl %di, %eax
240-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
241-
; X64-NEXT: fisubrl -{{[0-9]+}}(%rsp)
237+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
238+
; X64-NEXT: fisubrs -{{[0-9]+}}(%rsp)
242239
; X64-NEXT: retq
243240
%1 = sitofp i16 %a1 to x86_fp80
244241
%2 = fsub x86_fp80 %1, %a0
@@ -262,9 +259,9 @@ define x86_fp80 @fisubr_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
262259
; X64-LABEL: fisubr_fp80_i16_ld:
263260
; X64: # %bb.0:
264261
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
265-
; X64-NEXT: movswl (%rdi), %eax
266-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
267-
; X64-NEXT: fisubrl -{{[0-9]+}}(%rsp)
262+
; X64-NEXT: movzwl (%rdi), %eax
263+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
264+
; X64-NEXT: fisubrs -{{[0-9]+}}(%rsp)
268265
; X64-NEXT: retq
269266
%1 = load i16, i16 *%a1
270267
%2 = sitofp i16 %1 to x86_fp80
@@ -343,9 +340,8 @@ define x86_fp80 @fimul_fp80_i16(x86_fp80 %a0, i16 %a1) {
343340
; X64-LABEL: fimul_fp80_i16:
344341
; X64: # %bb.0:
345342
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
346-
; X64-NEXT: movswl %di, %eax
347-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
348-
; X64-NEXT: fimull -{{[0-9]+}}(%rsp)
343+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
344+
; X64-NEXT: fimuls -{{[0-9]+}}(%rsp)
349345
; X64-NEXT: retq
350346
%1 = sitofp i16 %a1 to x86_fp80
351347
%2 = fmul x86_fp80 %a0, %1
@@ -369,9 +365,9 @@ define x86_fp80 @fimul_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
369365
; X64-LABEL: fimul_fp80_i16_ld:
370366
; X64: # %bb.0:
371367
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
372-
; X64-NEXT: movswl (%rdi), %eax
373-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
374-
; X64-NEXT: fimull -{{[0-9]+}}(%rsp)
368+
; X64-NEXT: movzwl (%rdi), %eax
369+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
370+
; X64-NEXT: fimuls -{{[0-9]+}}(%rsp)
375371
; X64-NEXT: retq
376372
%1 = load i16, i16 *%a1
377373
%2 = sitofp i16 %1 to x86_fp80
@@ -450,9 +446,8 @@ define x86_fp80 @fidiv_fp80_i16(x86_fp80 %a0, i16 %a1) {
450446
; X64-LABEL: fidiv_fp80_i16:
451447
; X64: # %bb.0:
452448
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
453-
; X64-NEXT: movswl %di, %eax
454-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
455-
; X64-NEXT: fidivl -{{[0-9]+}}(%rsp)
449+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
450+
; X64-NEXT: fidivs -{{[0-9]+}}(%rsp)
456451
; X64-NEXT: retq
457452
%1 = sitofp i16 %a1 to x86_fp80
458453
%2 = fdiv x86_fp80 %a0, %1
@@ -476,9 +471,9 @@ define x86_fp80 @fidiv_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
476471
; X64-LABEL: fidiv_fp80_i16_ld:
477472
; X64: # %bb.0:
478473
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
479-
; X64-NEXT: movswl (%rdi), %eax
480-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
481-
; X64-NEXT: fidivl -{{[0-9]+}}(%rsp)
474+
; X64-NEXT: movzwl (%rdi), %eax
475+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
476+
; X64-NEXT: fidivs -{{[0-9]+}}(%rsp)
482477
; X64-NEXT: retq
483478
%1 = load i16, i16 *%a1
484479
%2 = sitofp i16 %1 to x86_fp80
@@ -557,9 +552,8 @@ define x86_fp80 @fidivr_fp80_i16(x86_fp80 %a0, i16 %a1) {
557552
; X64-LABEL: fidivr_fp80_i16:
558553
; X64: # %bb.0:
559554
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
560-
; X64-NEXT: movswl %di, %eax
561-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
562-
; X64-NEXT: fidivrl -{{[0-9]+}}(%rsp)
555+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
556+
; X64-NEXT: fidivrs -{{[0-9]+}}(%rsp)
563557
; X64-NEXT: retq
564558
%1 = sitofp i16 %a1 to x86_fp80
565559
%2 = fdiv x86_fp80 %1, %a0
@@ -583,9 +577,9 @@ define x86_fp80 @fidivr_fp80_i16_ld(x86_fp80 %a0, i16 *%a1) {
583577
; X64-LABEL: fidivr_fp80_i16_ld:
584578
; X64: # %bb.0:
585579
; X64-NEXT: fldt {{[0-9]+}}(%rsp)
586-
; X64-NEXT: movswl (%rdi), %eax
587-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
588-
; X64-NEXT: fidivrl -{{[0-9]+}}(%rsp)
580+
; X64-NEXT: movzwl (%rdi), %eax
581+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
582+
; X64-NEXT: fidivrs -{{[0-9]+}}(%rsp)
589583
; X64-NEXT: retq
590584
%1 = load i16, i16 *%a1
591585
%2 = sitofp i16 %1 to x86_fp80

‎llvm/test/CodeGen/X86/fp-cvt.ll

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -615,9 +615,8 @@ define x86_fp80 @sitofp_fp80_i16(i16 %a0) nounwind {
615615
;
616616
; X64-LABEL: sitofp_fp80_i16:
617617
; X64: # %bb.0:
618-
; X64-NEXT: movswl %di, %eax
619-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
620-
; X64-NEXT: fildl -{{[0-9]+}}(%rsp)
618+
; X64-NEXT: movw %di, -{{[0-9]+}}(%rsp)
619+
; X64-NEXT: filds -{{[0-9]+}}(%rsp)
621620
; X64-NEXT: retq
622621
%1 = sitofp i16 %a0 to x86_fp80
623622
ret x86_fp80 %1
@@ -636,9 +635,9 @@ define x86_fp80 @sitofp_fp80_i16_ld(i16 *%a0) nounwind {
636635
;
637636
; X64-LABEL: sitofp_fp80_i16_ld:
638637
; X64: # %bb.0:
639-
; X64-NEXT: movswl (%rdi), %eax
640-
; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
641-
; X64-NEXT: fildl -{{[0-9]+}}(%rsp)
638+
; X64-NEXT: movzwl (%rdi), %eax
639+
; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
640+
; X64-NEXT: filds -{{[0-9]+}}(%rsp)
642641
; X64-NEXT: retq
643642
%1 = load i16, i16 *%a0
644643
%2 = sitofp i16 %1 to x86_fp80

0 commit comments

Comments
 (0)