@@ -223,56 +223,43 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ShiftOp , MVT::i64 , Custom);
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}
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- // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
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- // operation.
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- setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
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- setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
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-
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if (!Subtarget.useSoftFloat()) {
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- // We have an algorithm for SSE2->double, and we turn this into a
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- // 64-bit FILD followed by conditional FADD for other targets.
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- setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
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+ // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
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+ // operation.
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+ setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
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+ setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
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// We have an algorithm for SSE2, and we turn this into a 64-bit
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// FILD or VCVTUSI2SS/SD for other targets.
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- setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
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- }
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-
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- // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
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- // this operation.
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- setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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+ setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
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+ // We have an algorithm for SSE2->double, and we turn this into a
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+ // 64-bit FILD followed by conditional FADD for other targets.
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+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
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- if (!Subtarget.useSoftFloat()) {
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+ // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
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+ // this operation.
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+ setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
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// SSE has no i16 to fp conversion, only i32.
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- if (X86ScalarSSEf32) {
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- setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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- // f32 and f64 cases are Legal, f80 case is not
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- setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
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- } else {
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- setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
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- setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
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- }
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- }
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-
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- // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
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- // this operation.
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- setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
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-
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- if (!Subtarget.useSoftFloat()) {
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+ setOperationAction(ISD::SINT_TO_FP, MVT::i16, X86ScalarSSEf32 ? Promote
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+ : Custom);
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+ // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
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+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
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// are Legal, f80 is custom lowered.
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- setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
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- setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
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+ setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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- setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
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- setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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- }
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-
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- // Handle FP_TO_UINT by promoting the destination to a larger signed
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- // conversion.
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- setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
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- setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote );
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+ // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
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+ // this operation.
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+ setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
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+ setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
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+ setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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+ // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
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+ // are Legal, f80 is custom lowered.
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+ setOperationAction(ISD::FP_TO_SINT , MVT::i64, Custom );
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- if (!Subtarget.useSoftFloat()) {
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+ // Handle FP_TO_UINT by promoting the destination to a larger signed
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+ // conversion.
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+ setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
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+ setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
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}
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