[GlobalISel][X86] G_PHI support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312473 91177308-0d34-0410-b5e6-96231b3b80d8

Author: Igor Breger

lib/Target/X86/X86InstructionSelector.cpp

@@ -85,7 +85,7 @@ class X86InstructionSelector : public InstructionSelector {
                      MachineFunction &MF) const;
   bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
                         MachineFunction &MF) const;
-  bool selectImplicitDef(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
 
   // emit insert subreg instruction and insert it before MachineInstr &I
   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
@@ -290,13 +290,10 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
 
     if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
       return false;
-    if (Opcode == TargetOpcode::PHI)
-      return false;
 
     if (I.isCopy())
       return selectCopy(I, MRI);
 
-    // TODO: handle more cases - LOAD_STACK_GUARD, PHI
     return true;
   }
 
@@ -335,7 +332,7 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
     return true;
   if (selectCondBranch(I, MRI, MF))
     return true;
-  if (selectImplicitDef(I, MRI))
+  if (selectImplicitDefOrPHI(I, MRI))
     return true;
 
   return false;
@@ -1131,10 +1128,11 @@ bool X86InstructionSelector::selectCondBranch(MachineInstr &I,
   return true;
 }
 
-bool X86InstructionSelector::selectImplicitDef(MachineInstr &I,
-                                               MachineRegisterInfo &MRI) const {
+bool X86InstructionSelector::selectImplicitDefOrPHI(
+    MachineInstr &I, MachineRegisterInfo &MRI) const {
 
-  if (I.getOpcode() != TargetOpcode::G_IMPLICIT_DEF)
+  if (I.getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
+      I.getOpcode() != TargetOpcode::G_PHI)
     return false;
 
   unsigned DstReg = I.getOperand(0).getReg();
@@ -1150,7 +1148,11 @@ bool X86InstructionSelector::selectImplicitDef(MachineInstr &I,
     }
   }
 
-  I.setDesc(TII.get(X86::IMPLICIT_DEF));
+  if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
+    I.setDesc(TII.get(X86::IMPLICIT_DEF));
+  else
+    I.setDesc(TII.get(X86::PHI));
+
   return true;
 }
 

lib/Target/X86/X86LegalizerInfo.cpp

@@ -52,6 +52,11 @@ void X86LegalizerInfo::setLegalizerInfo32bit() {
   for (auto Ty : {p0, s1, s8, s16, s32})
     setAction({G_IMPLICIT_DEF, Ty}, Legal);
 
+  for (auto Ty : {s8, s16, s32, p0})
+    setAction({G_PHI, Ty}, Legal);
+
+  setAction({G_PHI, s1}, WidenScalar);
+
   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
     for (auto Ty : {s8, s16, s32})
       setAction({BinOp, Ty}, Legal);
@@ -118,6 +123,8 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
 
   setAction({G_IMPLICIT_DEF, s64}, Legal);
 
+  setAction({G_PHI, s64}, Legal);
+
   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
     setAction({BinOp, s64}, Legal);