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AMDGPU: Simplify FP8 conversion definitions. NFC. (llvm#83043)
Reals should inherit predicates from the corresponding Pseudo.
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3 files changed

+3
-6
lines changed

3 files changed

+3
-6
lines changed

llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -636,8 +636,8 @@ def VOPProfile_Base_CVT_F32_F8_OpSel : VOPProfile<[f32, i32, untyped, untyped]>
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let Src1VOP3DPP = Src1RC64;
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}
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639-
let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 0,
640-
SchedRW = [WriteFloatCvt] in {
639+
let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts],
640+
mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {
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defm V_CVT_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_f32_fp8_op_sel", VOPProfile_Base_CVT_F32_F8_OpSel>;
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defm V_CVT_F32_BF8_OP_SEL : VOP1Inst<"v_cvt_f32_bf8_op_sel", VOPProfile_Base_CVT_F32_F8_OpSel>;
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defm V_CVT_PK_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_pk_f32_fp8_op_sel", VOPProfile_Base_CVT_PK_F32_F8_OpSel>;
@@ -1422,12 +1422,10 @@ defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>;
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let AssemblerPredicate = isGFX940Plus in
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defm V_MOV_B64 : VOP1_Real_gfx9 <0x38>;
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1425-
let OtherPredicates = [HasFP8ConversionInsts] in {
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defm V_CVT_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x54>;
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defm V_CVT_F32_BF8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x55>;
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defm V_CVT_PK_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x56>;
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defm V_CVT_PK_F32_BF8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x57>;
1430-
}
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//===----------------------------------------------------------------------===//
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// GFX10

llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1647,9 +1647,7 @@ defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
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defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>;
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1650-
let OtherPredicates = [HasFP8ConversionInsts] in {
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defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>;
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defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>;
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defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>;
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defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;
1655-
}

llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -670,6 +670,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
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let SubtargetPredicate = HasSDWA9;
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let AssemblerPredicate = HasSDWA9;
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let OtherPredicates = ps.OtherPredicates;
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let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
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AMDGPUAsmVariants.Disable);
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let DecoderNamespace = "GFX9";

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