@@ -127,7 +127,6 @@ class SIFixSGPRCopies {
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unsigned NextVGPRToSGPRCopyID = 0 ;
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MapVector<unsigned , V2SCopyInfo> V2SCopies;
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DenseMap<MachineInstr *, SetVector<unsigned >> SiblingPenalty;
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- DenseSet<MachineInstr *> PHISources;
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public:
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MachineRegisterInfo *MRI;
@@ -692,8 +691,10 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
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TII->get (AMDGPU::COPY), NewDst)
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.addReg (MO.getReg ());
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MO.setReg (NewDst);
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+
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+ // FIXME: We are transitively revisiting users of this
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+ // instruction for every input.
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analyzeVGPRToSGPRCopy (NewCopy);
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- PHISources.insert (NewCopy);
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}
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}
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}
@@ -800,7 +801,6 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
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RegSequences.clear ();
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PHINodes.clear ();
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S2VCopies.clear ();
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- PHISources.clear ();
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return true ;
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}
@@ -926,13 +926,13 @@ bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI,
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}
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void SIFixSGPRCopies::analyzeVGPRToSGPRCopy (MachineInstr* MI) {
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- if (PHISources.contains (MI))
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- return ;
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Register DstReg = MI->getOperand (0 ).getReg ();
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const TargetRegisterClass *DstRC = MRI->getRegClass (DstReg);
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V2SCopyInfo Info (getNextVGPRToSGPRCopyId (), MI,
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TRI->getRegSizeInBits (*DstRC));
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+ V2SCopies[Info.ID ] = Info;
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+
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SmallVector<MachineInstr *, 8 > AnalysisWorklist;
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// Needed because the SSA is not a tree but a graph and may have
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// forks and joins. We should not then go same way twice.
@@ -971,18 +971,16 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
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}
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} else if (Inst->getNumExplicitDefs () != 0 ) {
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Register Reg = Inst->getOperand (0 ).getReg ();
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- if (Reg. isVirtual () && TRI->isSGPRReg (*MRI, Reg) && !TII->isVALU (*Inst)) {
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+ if (TRI->isSGPRReg (*MRI, Reg) && !TII->isVALU (*Inst))
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for (auto &U : MRI->use_instructions (Reg))
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Users.push_back (&U);
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- }
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}
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for (auto *U : Users) {
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if (TII->isSALU (*U))
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Info.SChain .insert (U);
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AnalysisWorklist.push_back (U);
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}
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}
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- V2SCopies[Info.ID ] = Info;
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}
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// The main function that computes the VGPR to SGPR copy score
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