Skip to content
This repository was archived by the owner on Mar 28, 2020. It is now read-only.

Commit 005af43

Browse files
Petar AvramovicPetar Avramovic
Petar Avramovic
authored and
Petar Avramovic
committed
[MIPS GlobalISel] Select any extending load and truncating store
Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353520 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 2fdf6f9 commit 005af43

File tree

9 files changed

+552
-76
lines changed

9 files changed

+552
-76
lines changed

‎lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1208,13 +1208,6 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
12081208
return Legalized;
12091209

12101210
case TargetOpcode::G_LOAD:
1211-
// For some types like i24, we might try to widen to i32. To properly handle
1212-
// this we should be using a dedicated extending load, until then avoid
1213-
// trying to legalize.
1214-
if (alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) !=
1215-
WideTy.getSizeInBits())
1216-
return UnableToLegalize;
1217-
LLVM_FALLTHROUGH;
12181211
case TargetOpcode::G_SEXTLOAD:
12191212
case TargetOpcode::G_ZEXTLOAD:
12201213
Observer.changingInstr(MI);

‎lib/Target/Mips/MipsInstructionSelector.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,10 +96,15 @@ static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
9696
switch (MemSizeInBytes) {
9797
case 4:
9898
return Mips::SW;
99+
case 2:
100+
return Mips::SH;
101+
case 1:
102+
return Mips::SB;
99103
default:
100104
return Opc;
101105
}
102106
else
107+
// Unspecified extending load is selected into zeroExtending load.
103108
switch (MemSizeInBytes) {
104109
case 4:
105110
return Mips::LW;

‎lib/Target/Mips/MipsLegalizerInfo.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
3636
.lowerFor({{s32, s1}});
3737

3838
getActionDefinitionsBuilder({G_LOAD, G_STORE})
39-
.legalForCartesianProduct({p0, s32}, {p0});
39+
.legalForTypesWithMemSize({{s32, p0, 8},
40+
{s32, p0, 16},
41+
{s32, p0, 32},
42+
{p0, p0, 32}})
43+
.minScalar(0, s32);
4044

4145
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
4246
.legalForTypesWithMemSize({{s32, p0, 8},

‎test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir

Lines changed: 79 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,24 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
3-
# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
4-
5-
# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_sextload_flat_i32_i8)
6-
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI
3+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI
74
---
85
name: test_sextload_flat_i32_i8
96
body: |
107
bb.0:
118
liveins: $vgpr0_vgpr1
129
13-
; CHECK-LABEL: name: test_sextload_flat_i32_i8
14-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
15-
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
16-
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
10+
; SI-LABEL: name: test_sextload_flat_i32_i8
11+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
12+
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
13+
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
14+
; VI-LABEL: name: test_sextload_flat_i32_i8
15+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
16+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
17+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
18+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
19+
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
20+
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
21+
; VI: $vgpr0 = COPY [[ASHR]](s32)
1722
%0:_(p0) = COPY $vgpr0_vgpr1
1823
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
1924
$vgpr0 = COPY %1
@@ -24,11 +29,19 @@ body: |
2429
bb.0:
2530
liveins: $vgpr0_vgpr1
2631
27-
; CHECK-LABEL: name: test_sextload_flat_i32_i16
28-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
29-
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
30-
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
31-
%0:_(p0) = COPY $vgpr0_vgpr1
32+
; SI-LABEL: name: test_sextload_flat_i32_i16
33+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
34+
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
35+
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
36+
; VI-LABEL: name: test_sextload_flat_i32_i16
37+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
38+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
39+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
40+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
41+
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
42+
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
43+
; VI: $vgpr0 = COPY [[ASHR]](s32)
44+
%0:_(p0) = COPY $vgpr0_vgpr1
3245
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
3346
$vgpr0 = COPY %1
3447
...
@@ -38,11 +51,20 @@ body: |
3851
bb.0:
3952
liveins: $vgpr0_vgpr1
4053
41-
; CHECK-LABEL: name: test_sextload_flat_i31_i8
42-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
43-
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
44-
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
45-
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
54+
; SI-LABEL: name: test_sextload_flat_i31_i8
55+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
56+
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
57+
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
58+
; SI: $vgpr0 = COPY [[COPY1]](s32)
59+
; VI-LABEL: name: test_sextload_flat_i31_i8
60+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
61+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
62+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
63+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
64+
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
65+
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
66+
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
67+
; VI: $vgpr0 = COPY [[COPY2]](s32)
4668
%0:_(p0) = COPY $vgpr0_vgpr1
4769
%1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
4870
%2:_(s32) = G_ANYEXT %1
@@ -54,11 +76,20 @@ body: |
5476
bb.0:
5577
liveins: $vgpr0_vgpr1
5678
57-
; CHECK-LABEL: name: test_sextload_flat_i64_i8
58-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
59-
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
60-
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
61-
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
79+
; SI-LABEL: name: test_sextload_flat_i64_i8
80+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
81+
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
82+
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
83+
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
84+
; VI-LABEL: name: test_sextload_flat_i64_i8
85+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
86+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
87+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
88+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
89+
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
90+
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
91+
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
92+
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
6293
%0:_(p0) = COPY $vgpr0_vgpr1
6394
%1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
6495
$vgpr0_vgpr1 = COPY %1
@@ -69,11 +100,20 @@ body: |
69100
bb.0:
70101
liveins: $vgpr0_vgpr1
71102
72-
; CHECK-LABEL: name: test_sextload_flat_i64_i16
73-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
74-
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
75-
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
76-
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
103+
; SI-LABEL: name: test_sextload_flat_i64_i16
104+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
105+
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
106+
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
107+
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
108+
; VI-LABEL: name: test_sextload_flat_i64_i16
109+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
110+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
111+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
112+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
113+
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
114+
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
115+
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
116+
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
77117
%0:_(p0) = COPY $vgpr0_vgpr1
78118
%1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
79119
$vgpr0_vgpr1 = COPY %1
@@ -84,11 +124,16 @@ body: |
84124
bb.0:
85125
liveins: $vgpr0_vgpr1
86126
87-
; CHECK-LABEL: name: test_sextload_flat_i64_i32
88-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
89-
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
90-
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
91-
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
127+
; SI-LABEL: name: test_sextload_flat_i64_i32
128+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
129+
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
130+
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
131+
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
132+
; VI-LABEL: name: test_sextload_flat_i64_i32
133+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
134+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
135+
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
136+
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
92137
%0:_(p0) = COPY $vgpr0_vgpr1
93138
%1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 0)
94139
$vgpr0_vgpr1 = COPY %1

‎test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir

Lines changed: 74 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,23 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
3-
# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
4-
5-
# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_zextload_flat_i32_i8)
6-
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI
3+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI
74
---
85
name: test_zextload_flat_i32_i8
96
body: |
107
bb.0:
118
liveins: $vgpr0_vgpr1
129
13-
; CHECK-LABEL: name: test_zextload_flat_i32_i8
14-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
15-
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
16-
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
10+
; SI-LABEL: name: test_zextload_flat_i32_i8
11+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
12+
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
13+
; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
14+
; VI-LABEL: name: test_zextload_flat_i32_i8
15+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
16+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
17+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
18+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
19+
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
20+
; VI: $vgpr0 = COPY [[AND]](s32)
1721
%0:_(p0) = COPY $vgpr0_vgpr1
1822
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
1923
$vgpr0 = COPY %1
@@ -24,11 +28,18 @@ body: |
2428
bb.0:
2529
liveins: $vgpr0_vgpr1
2630
27-
; CHECK-LABEL: name: test_zextload_flat_i32_i16
28-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
29-
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
30-
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
31-
%0:_(p0) = COPY $vgpr0_vgpr1
31+
; SI-LABEL: name: test_zextload_flat_i32_i16
32+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
33+
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
34+
; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
35+
; VI-LABEL: name: test_zextload_flat_i32_i16
36+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
37+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
38+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
39+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
40+
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
41+
; VI: $vgpr0 = COPY [[AND]](s32)
42+
%0:_(p0) = COPY $vgpr0_vgpr1
3243
%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
3344
$vgpr0 = COPY %1
3445
...
@@ -38,11 +49,19 @@ body: |
3849
bb.0:
3950
liveins: $vgpr0_vgpr1
4051
41-
; CHECK-LABEL: name: test_zextload_flat_i31_i8
42-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
43-
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
44-
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
45-
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
52+
; SI-LABEL: name: test_zextload_flat_i31_i8
53+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
54+
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
55+
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
56+
; SI: $vgpr0 = COPY [[COPY1]](s32)
57+
; VI-LABEL: name: test_zextload_flat_i31_i8
58+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
59+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
60+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
61+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
62+
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
63+
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
64+
; VI: $vgpr0 = COPY [[COPY2]](s32)
4665
%0:_(p0) = COPY $vgpr0_vgpr1
4766
%1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
4867
%2:_(s32) = G_ANYEXT %1
@@ -54,11 +73,19 @@ body: |
5473
bb.0:
5574
liveins: $vgpr0_vgpr1
5675
57-
; CHECK-LABEL: name: test_zextload_flat_i64_i8
58-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
59-
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
60-
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
61-
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
76+
; SI-LABEL: name: test_zextload_flat_i64_i8
77+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
78+
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
79+
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
80+
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
81+
; VI-LABEL: name: test_zextload_flat_i64_i8
82+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
83+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
84+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
85+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
86+
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
87+
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
88+
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
6289
%0:_(p0) = COPY $vgpr0_vgpr1
6390
%1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
6491
$vgpr0_vgpr1 = COPY %1
@@ -69,11 +96,19 @@ body: |
6996
bb.0:
7097
liveins: $vgpr0_vgpr1
7198
72-
; CHECK-LABEL: name: test_zextload_flat_i64_i16
73-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
74-
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
75-
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
76-
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
99+
; SI-LABEL: name: test_zextload_flat_i64_i16
100+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
101+
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
102+
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
103+
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
104+
; VI-LABEL: name: test_zextload_flat_i64_i16
105+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
106+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
107+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
108+
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
109+
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
110+
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
111+
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
77112
%0:_(p0) = COPY $vgpr0_vgpr1
78113
%1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
79114
$vgpr0_vgpr1 = COPY %1
@@ -84,11 +119,16 @@ body: |
84119
bb.0:
85120
liveins: $vgpr0_vgpr1
86121
87-
; CHECK-LABEL: name: test_zextload_flat_i64_i32
88-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
89-
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
90-
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
91-
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
122+
; SI-LABEL: name: test_zextload_flat_i64_i32
123+
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
124+
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
125+
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
126+
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
127+
; VI-LABEL: name: test_zextload_flat_i64_i32
128+
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
129+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
130+
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
131+
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
92132
%0:_(p0) = COPY $vgpr0_vgpr1
93133
%1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 0)
94134
$vgpr0_vgpr1 = COPY %1

0 commit comments

Comments
 (0)