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Commit 07fb294

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GlobalISel: deal with new G_PTR_MASK instruction on AArch64.
It's just an AND-immediate instruction for us, surprisingly simple to select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295104 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/AArch64/AArch64InstructionSelector.cpp

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@@ -816,6 +816,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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case TargetOpcode::G_PTR_MASK: {
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uint64_t Align = I.getOperand(2).getImm();
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if (Align >= 64 || Align == 0)
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return false;
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uint64_t Mask = ~((1ULL << Align) - 1);
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I.setDesc(TII.get(AArch64::ANDXri));
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I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64));
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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case TargetOpcode::G_PTRTOINT:
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case TargetOpcode::G_TRUNC: {
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const LLT DstTy = MRI.getType(I.getOperand(0).getReg());

lib/Target/AArch64/AArch64LegalizerInfo.cpp

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@@ -52,6 +52,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() {
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for (auto Ty : {s1, s8, s16, s32})
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setAction({G_GEP, 1, Ty}, WidenScalar);
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setAction({G_PTR_MASK, p0}, Legal);
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for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV}) {
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for (auto Ty : {s32, s64})
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setAction({BinOp, Ty}, Legal);

test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

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@@ -114,6 +114,8 @@
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define i8* @gep(i8* %in) { ret i8* undef }
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define i8* @ptr_mask(i8* %in) { ret i8* undef }
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@var_local = global i8 0
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define i8* @global_local() { ret i8* undef }
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@@ -2043,6 +2045,21 @@ body: |
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%2(p0) = G_GEP %0, %1(s64)
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...
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---
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# CHECK-LABEL: name: ptr_mask
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name: ptr_mask
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legalized: true
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regBankSelected: true
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# CHECK: body:
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# CHECK: %1 = ANDXri %0, 8060
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body: |
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bb.0:
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liveins: %x0
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%0:gpr(p0) = COPY %x0
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%1:gpr(p0) = G_PTR_MASK %0, 3
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...
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---
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# Global defined in the same linkage unit so no GOT is needed
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# CHECK-LABEL: name: global_local

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