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Commit 15d116a

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dsandersllvmdsandersllvm
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[mips] Range check simm11 and mem_simm11.
Summary: ldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem is that they don't trigger the custom parser because all the candidates are disabled by feature bits. On all other subtargets, the diagnostics are accurate but are subject to the usual issues of needing to report multiple ways to correct the code (e.g. smaller offset, enable a CPU feature) but only being able to report one error. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265018 91177308-0d34-0410-b5e6-96231b3b80d8
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6 files changed

+31
-14
lines changed

6 files changed

+31
-14
lines changed

‎lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3786,6 +3786,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
37863786
case Match_SImm10_0:
37873787
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
37883788
"expected 10-bit signed immediate");
3789+
case Match_SImm11_0:
3790+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3791+
"expected 11-bit signed immediate");
37893792
case Match_UImm16:
37903793
case Match_UImm16_Relaxed:
37913794
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
@@ -3814,6 +3817,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
38143817
case Match_MemSImm10Lsl3:
38153818
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
38163819
"expected memory with 13-bit signed offset and multiple of 8");
3820+
case Match_MemSImm11:
3821+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3822+
"expected memory with 11-bit signed offset");
38173823
}
38183824

38193825
llvm_unreachable("Implement any new match types added!");

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -479,11 +479,13 @@ def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
479479
let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];
480480
let DiagnosticType = "SImm10_Lsl2";
481481
}
482+
def ConstantSImm11AsmOperandClass
483+
: ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>;
482484
def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {
483485
let Name = "SImm10Lsl1";
484486
let RenderMethod = "addImmOperands";
485487
let PredicateMethod = "isScaledSImm<10, 1>";
486-
let SuperClasses = [ConstantSImm10Lsl2AsmOperandClass];
488+
let SuperClasses = [ConstantSImm11AsmOperandClass];
487489
let DiagnosticType = "SImm10_Lsl1";
488490
}
489491
def ConstantUImm10AsmOperandClass
@@ -598,8 +600,6 @@ def calltarget : Operand<iPTR> {
598600

599601
def imm64: Operand<i64>;
600602

601-
def simm11 : Operand<i32>;
602-
603603
def simm16 : Operand<i32> {
604604
let DecoderMethod= "DecodeSimm16";
605605
}
@@ -763,7 +763,7 @@ foreach I = {1, 2, 3, 4, 5, 6, 8} in
763763
}
764764

765765
// Signed operands
766-
foreach I = {4, 5, 6, 9, 10} in
766+
foreach I = {4, 5, 6, 9, 10, 11} in
767767
def simm # I : Operand<i32> {
768768
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
769769
let ParserMatchClass =
@@ -854,6 +854,7 @@ def MipsMemSimm11AsmOperand : AsmOperandClass {
854854
let RenderMethod = "addMemOperands";
855855
let ParserMethod = "parseMemOperand";
856856
let PredicateMethod = "isMemWithSimmOffset<11>";
857+
let DiagnosticType = "MemSImm11";
857858
}
858859

859860
def MipsMemSimm16AsmOperand : AsmOperandClass {
@@ -1150,15 +1151,17 @@ class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
11501151
// COP2 Load/Store
11511152
class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
11521153
SDPatternOperator OpNode= null_frag> :
1153-
InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1154+
InstSE<(outs RC:$rt), (ins mem_simm16:$addr),
1155+
!strconcat(opstr, "\t$rt, $addr"),
11541156
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
11551157
let DecoderMethod = "DecodeFMem2";
11561158
let mayLoad = 1;
11571159
}
11581160

11591161
class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
11601162
SDPatternOperator OpNode= null_frag> :
1161-
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1163+
InstSE<(outs), (ins RC:$rt, mem_simm16:$addr),
1164+
!strconcat(opstr, "\t$rt, $addr"),
11621165
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
11631166
let DecoderMethod = "DecodeFMem2";
11641167
let mayStore = 1;

‎test/MC/Mips/mips1/invalid-mips2-wrong-error.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,12 @@
77

88
.set noat
99
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
11+
ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
1112
ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1213
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1314
sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1415
sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
17+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
1618
sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips1/invalid-mips3-wrong-error.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@
88
.set noat
99
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1010
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
12+
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
1213
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1314
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1415
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -18,6 +19,7 @@
1819
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1920
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2021
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
21-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
22+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
23+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
2224
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2325
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips1/invalid-mips4-wrong-error.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010
bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1111
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1212
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13+
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
14+
ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
1415
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1516
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1617
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -20,6 +21,7 @@
2021
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2122
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2223
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
23-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24+
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
25+
sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
2426
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2527
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎test/MC/Mips/mips32r6/invalid.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,6 @@ local_label:
1212
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
1313
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
1414
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
15-
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16-
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1715
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1816
break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
1917
break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
@@ -35,6 +33,8 @@ local_label:
3533
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
3634
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
3735
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
36+
ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
37+
ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
3838
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
3939
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
4040
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
@@ -47,3 +47,5 @@ local_label:
4747
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
4848
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
4949
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
50+
sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
51+
sdc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled

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