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[x86] add negate-i1 run for 32-bit target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284124 91177308-0d34-0410-b5e6-96231b3b80d8
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test/CodeGen/X86/negate-i1.ll

Lines changed: 112 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1,99 +1,160 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
2+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
3+
; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
34

45
define i8 @select_i8_neg1_or_0(i1 %a) {
5-
; CHECK-LABEL: select_i8_neg1_or_0:
6-
; CHECK: # BB#0:
7-
; CHECK-NEXT: shlb $7, %dil
8-
; CHECK-NEXT: sarb $7, %dil
9-
; CHECK-NEXT: movl %edi, %eax
10-
; CHECK-NEXT: retq
6+
; X64-LABEL: select_i8_neg1_or_0:
7+
; X64: # BB#0:
8+
; X64-NEXT: shlb $7, %dil
9+
; X64-NEXT: sarb $7, %dil
10+
; X64-NEXT: movl %edi, %eax
11+
; X64-NEXT: retq
12+
;
13+
; X32-LABEL: select_i8_neg1_or_0:
14+
; X32: # BB#0:
15+
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
16+
; X32-NEXT: shlb $7, %al
17+
; X32-NEXT: sarb $7, %al
18+
; X32-NEXT: retl
1119
;
1220
%b = sext i1 %a to i8
1321
ret i8 %b
1422
}
1523

1624
define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
17-
; CHECK-LABEL: select_i8_neg1_or_0_zeroext:
18-
; CHECK: # BB#0:
19-
; CHECK-NEXT: shlb $7, %dil
20-
; CHECK-NEXT: sarb $7, %dil
21-
; CHECK-NEXT: movl %edi, %eax
22-
; CHECK-NEXT: retq
25+
; X64-LABEL: select_i8_neg1_or_0_zeroext:
26+
; X64: # BB#0:
27+
; X64-NEXT: shlb $7, %dil
28+
; X64-NEXT: sarb $7, %dil
29+
; X64-NEXT: movl %edi, %eax
30+
; X64-NEXT: retq
31+
;
32+
; X32-LABEL: select_i8_neg1_or_0_zeroext:
33+
; X32: # BB#0:
34+
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
35+
; X32-NEXT: shlb $7, %al
36+
; X32-NEXT: sarb $7, %al
37+
; X32-NEXT: retl
2338
;
2439
%b = sext i1 %a to i8
2540
ret i8 %b
2641
}
2742

2843
define i16 @select_i16_neg1_or_0(i1 %a) {
29-
; CHECK-LABEL: select_i16_neg1_or_0:
30-
; CHECK: # BB#0:
31-
; CHECK-NEXT: shll $15, %edi
32-
; CHECK-NEXT: sarw $15, %di
33-
; CHECK-NEXT: movl %edi, %eax
34-
; CHECK-NEXT: retq
44+
; X64-LABEL: select_i16_neg1_or_0:
45+
; X64: # BB#0:
46+
; X64-NEXT: shll $15, %edi
47+
; X64-NEXT: sarw $15, %di
48+
; X64-NEXT: movl %edi, %eax
49+
; X64-NEXT: retq
50+
;
51+
; X32-LABEL: select_i16_neg1_or_0:
52+
; X32: # BB#0:
53+
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
54+
; X32-NEXT: shll $15, %eax
55+
; X32-NEXT: sarw $15, %ax
56+
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
57+
; X32-NEXT: retl
3558
;
3659
%b = sext i1 %a to i16
3760
ret i16 %b
3861
}
3962

4063
define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
41-
; CHECK-LABEL: select_i16_neg1_or_0_zeroext:
42-
; CHECK: # BB#0:
43-
; CHECK-NEXT: movzbl %dil, %eax
44-
; CHECK-NEXT: shll $15, %eax
45-
; CHECK-NEXT: sarw $15, %ax
46-
; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
47-
; CHECK-NEXT: retq
64+
; X64-LABEL: select_i16_neg1_or_0_zeroext:
65+
; X64: # BB#0:
66+
; X64-NEXT: movzbl %dil, %eax
67+
; X64-NEXT: shll $15, %eax
68+
; X64-NEXT: sarw $15, %ax
69+
; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
70+
; X64-NEXT: retq
71+
;
72+
; X32-LABEL: select_i16_neg1_or_0_zeroext:
73+
; X32: # BB#0:
74+
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
75+
; X32-NEXT: shll $15, %eax
76+
; X32-NEXT: sarw $15, %ax
77+
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
78+
; X32-NEXT: retl
4879
;
4980
%b = sext i1 %a to i16
5081
ret i16 %b
5182
}
5283

5384
define i32 @select_i32_neg1_or_0(i1 %a) {
54-
; CHECK-LABEL: select_i32_neg1_or_0:
55-
; CHECK: # BB#0:
56-
; CHECK-NEXT: shll $31, %edi
57-
; CHECK-NEXT: sarl $31, %edi
58-
; CHECK-NEXT: movl %edi, %eax
59-
; CHECK-NEXT: retq
85+
; X64-LABEL: select_i32_neg1_or_0:
86+
; X64: # BB#0:
87+
; X64-NEXT: shll $31, %edi
88+
; X64-NEXT: sarl $31, %edi
89+
; X64-NEXT: movl %edi, %eax
90+
; X64-NEXT: retq
91+
;
92+
; X32-LABEL: select_i32_neg1_or_0:
93+
; X32: # BB#0:
94+
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
95+
; X32-NEXT: shll $31, %eax
96+
; X32-NEXT: sarl $31, %eax
97+
; X32-NEXT: retl
6098
;
6199
%b = sext i1 %a to i32
62100
ret i32 %b
63101
}
64102

65103
define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
66-
; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
67-
; CHECK: # BB#0:
68-
; CHECK-NEXT: movzbl %dil, %eax
69-
; CHECK-NEXT: shll $31, %eax
70-
; CHECK-NEXT: sarl $31, %eax
71-
; CHECK-NEXT: retq
104+
; X64-LABEL: select_i32_neg1_or_0_zeroext:
105+
; X64: # BB#0:
106+
; X64-NEXT: movzbl %dil, %eax
107+
; X64-NEXT: shll $31, %eax
108+
; X64-NEXT: sarl $31, %eax
109+
; X64-NEXT: retq
110+
;
111+
; X32-LABEL: select_i32_neg1_or_0_zeroext:
112+
; X32: # BB#0:
113+
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
114+
; X32-NEXT: shll $31, %eax
115+
; X32-NEXT: sarl $31, %eax
116+
; X32-NEXT: retl
72117
;
73118
%b = sext i1 %a to i32
74119
ret i32 %b
75120
}
76121

77122
define i64 @select_i64_neg1_or_0(i1 %a) {
78-
; CHECK-LABEL: select_i64_neg1_or_0:
79-
; CHECK: # BB#0:
80-
; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
81-
; CHECK-NEXT: shlq $63, %rdi
82-
; CHECK-NEXT: sarq $63, %rdi
83-
; CHECK-NEXT: movq %rdi, %rax
84-
; CHECK-NEXT: retq
123+
; X64-LABEL: select_i64_neg1_or_0:
124+
; X64: # BB#0:
125+
; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
126+
; X64-NEXT: shlq $63, %rdi
127+
; X64-NEXT: sarq $63, %rdi
128+
; X64-NEXT: movq %rdi, %rax
129+
; X64-NEXT: retq
130+
;
131+
; X32-LABEL: select_i64_neg1_or_0:
132+
; X32: # BB#0:
133+
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
134+
; X32-NEXT: shll $31, %eax
135+
; X32-NEXT: sarl $31, %eax
136+
; X32-NEXT: movl %eax, %edx
137+
; X32-NEXT: retl
85138
;
86139
%b = sext i1 %a to i64
87140
ret i64 %b
88141
}
89142

90143
define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
91-
; CHECK-LABEL: select_i64_neg1_or_0_zeroext:
92-
; CHECK: # BB#0:
93-
; CHECK-NEXT: movzbl %dil, %eax
94-
; CHECK-NEXT: shlq $63, %rax
95-
; CHECK-NEXT: sarq $63, %rax
96-
; CHECK-NEXT: retq
144+
; X64-LABEL: select_i64_neg1_or_0_zeroext:
145+
; X64: # BB#0:
146+
; X64-NEXT: movzbl %dil, %eax
147+
; X64-NEXT: shlq $63, %rax
148+
; X64-NEXT: sarq $63, %rax
149+
; X64-NEXT: retq
150+
;
151+
; X32-LABEL: select_i64_neg1_or_0_zeroext:
152+
; X32: # BB#0:
153+
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
154+
; X32-NEXT: shll $31, %eax
155+
; X32-NEXT: sarl $31, %eax
156+
; X32-NEXT: movl %eax, %edx
157+
; X32-NEXT: retl
97158
;
98159
%b = sext i1 %a to i64
99160
ret i64 %b

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