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Commit 20d3d70

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Simon Dardis
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Revert "[mips] Add rsqrt, recip for MIPS"
This reverts commit r282485 which contain two patches instead of one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283327 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 8bebbdc commit 20d3d70

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‎lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -995,7 +995,7 @@ class MipsOperand : public MCParsedAsmOperand {
995995
void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
996996
assert(N == 1 && "Invalid number of operands!");
997997
uint64_t Imm = getConstantImm() - Offset;
998-
Imm &= (1ULL << Bits) - 1;
998+
Imm &= (1 << Bits) - 1;
999999
Imm += Offset;
10001000
Imm += AdjustOffset;
10011001
Inst.addOperand(MCOperand::createImm(Imm));
@@ -1093,8 +1093,7 @@ class MipsOperand : public MCParsedAsmOperand {
10931093
bool isRegIdx() const { return Kind == k_RegisterIndex; }
10941094
bool isImm() const override { return Kind == k_Immediate; }
10951095
bool isConstantImm() const {
1096-
int64_t Res;
1097-
return isImm() && getImm()->evaluateAsAbsolute(Res);
1096+
return isImm() && isa<MCConstantExpr>(getImm());
10981097
}
10991098
bool isConstantImmz() const {
11001099
return isConstantImm() && getConstantImm() == 0;
@@ -1265,9 +1264,7 @@ class MipsOperand : public MCParsedAsmOperand {
12651264

12661265
int64_t getConstantImm() const {
12671266
const MCExpr *Val = getImm();
1268-
int64_t Value = 0;
1269-
(void)Val->evaluateAsAbsolute(Value);
1270-
return Value;
1267+
return static_cast<const MCConstantExpr *>(Val)->getValue();
12711268
}
12721269

12731270
MipsOperand *getMemBase() const {
@@ -4054,9 +4051,6 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
40544051
case Match_SImm32_Relaxed:
40554052
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
40564053
"expected 32-bit signed immediate");
4057-
case Match_UImm32_Coerced:
4058-
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
4059-
"expected 32-bit immediate");
40604054
case Match_MemSImm9:
40614055
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
40624056
"expected memory with 9-bit signed offset");

‎lib/Target/Mips/MicroMips32r6InstrInfo.td

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,8 @@ class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
186186
class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
187187
class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
188188
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
189+
class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
190+
class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
189191
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
190192
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
191193
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
@@ -196,6 +198,8 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
196198
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
197199
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
198200
class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
201+
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
202+
class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
199203
class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
200204
class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
201205
class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
@@ -1114,6 +1118,14 @@ class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
11141118
II_SQRT_S, fsqrt>;
11151119
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
11161120
II_SQRT_D, fsqrt>;
1121+
class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
1122+
FGR32Opnd, II_TRUNC>;
1123+
class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
1124+
AFGR64Opnd, II_TRUNC>;
1125+
class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
1126+
FGR32Opnd, II_ROUND>;
1127+
class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
1128+
II_ROUND>;
11171129
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
11181130
FGR32Opnd, II_ROUND>;
11191131
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
@@ -1652,6 +1664,10 @@ def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
16521664
ISA_MICROMIPS32R6;
16531665
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
16541666
ISA_MICROMIPS32R6;
1667+
def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1668+
ISA_MICROMIPS32R6;
1669+
def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1670+
ISA_MICROMIPS32R6;
16551671
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
16561672
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
16571673
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1692,6 +1708,9 @@ def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
16921708
def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
16931709
def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
16941710
def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1711+
def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
1712+
ISA_MICROMIPS32R6;
1713+
def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
16951714
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
16961715
ISA_MICROMIPS32R6;
16971716
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;

‎lib/Target/Mips/MicroMipsInstrFPU.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -141,16 +141,6 @@ let AdditionalPredicates = [InMicroMips] in {
141141
MFC1_FM_MM<0x40>;
142142
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
143143
MFC1_FM_MM<0x60>;
144-
def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
145-
II_RECIP_S>,
146-
ROUND_W_FM_MM<0b0, 0b01001000>;
147-
def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
148-
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
149-
def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
150-
II_RECIP_S>,
151-
ROUND_W_FM_MM<0b0, 0b00001000>;
152-
def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
153-
II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
154144
}
155145
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
156146
def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,

‎lib/Target/Mips/MipsInstrFPU.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -284,16 +284,6 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
284284
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
285285
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
286286

287-
let AdditionalPredicates = [NotInMicroMips] in {
288-
def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
289-
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
290-
def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
291-
ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
292-
def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
293-
ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
294-
def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
295-
ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
296-
}
297287
let DecoderNamespace = "Mips64" in {
298288
let AdditionalPredicates = [NotInMicroMips] in {
299289
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 3 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -300,9 +300,6 @@ class INSN_MIPS3_32_NOT_32R6_64R6 {
300300
// The portions of MIPS-III that were also added to MIPS32
301301
class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
302302

303-
// The portions of MIPS-IV that were also added to MIPS32.
304-
class INSN_MIPS4_32 { list <Predicate> InsnPredicates = [HasMips4_32]; }
305-
306303
// The portions of MIPS-IV that were also added to MIPS32 but were removed in
307304
// MIPS32r6 and MIPS64r6.
308305
class INSN_MIPS4_32_NOT_32R6_64R6 {
@@ -315,11 +312,6 @@ class INSN_MIPS4_32R2_NOT_32R6_64R6 {
315312
list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
316313
}
317314

318-
// The portions of MIPS-IV that were also added to MIPS32r2.
319-
class INSN_MIPS4_32R2 {
320-
list<Predicate> InsnPredicates = [HasMips4_32r2];
321-
}
322-
323315
// The portions of MIPS-V that were also added to MIPS32r2 but were removed in
324316
// MIPS32r6 and MIPS64r6.
325317
class INSN_MIPS5_32R2_NOT_32R6_64R6 {
@@ -467,16 +459,6 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
467459
let DiagnosticType = "UImm" # Bits;
468460
}
469461

470-
// Generic case - only to support certain assembly pseudo instructions.
471-
class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
472-
: AsmOperandClass {
473-
let Name = "ImmAny";
474-
let RenderMethod = "addConstantUImmOperands<32>";
475-
let PredicateMethod = "isSImm<" # Bits # ">";
476-
let SuperClasses = Supers;
477-
let DiagnosticType = "ImmAny";
478-
}
479-
480462
// AsmOperandClasses require a strict ordering which is difficult to manage
481463
// as a hierarchy. Instead, we use a linear ordering and impose an order that
482464
// is in some places arbitrary.
@@ -500,13 +482,8 @@ class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
500482
// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
501483
// This is entirely arbitrary. We need an ordering and what we pick is
502484
// unimportant since only one is possible for a given mnemonic.
503-
504-
def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
505-
let Name = "UImm32_Coerced";
506-
let DiagnosticType = "UImm32_Coerced";
507-
}
508485
def SImm32RelaxedAsmOperandClass
509-
: SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
486+
: SImmAsmOperandClass<32, []> {
510487
let Name = "SImm32_Relaxed";
511488
let PredicateMethod = "isAnyImm<32>";
512489
let DiagnosticType = "SImm32_Relaxed";
@@ -530,8 +507,6 @@ def UImm16RelaxedAsmOperandClass
530507
let PredicateMethod = "isAnyImm<16>";
531508
let DiagnosticType = "UImm16_Relaxed";
532509
}
533-
// FIXME: One of these should probably have UImm16AsmOperandClass as the
534-
// superclass instead of UImm16RelaxedasmOPerandClass.
535510
def UImm16AsmOperandClass
536511
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
537512
def SImm16RelaxedAsmOperandClass
@@ -889,10 +864,6 @@ def simm16_64 : Operand<i64> {
889864
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
890865
}
891866

892-
// like simm32 but coerces simm32 to uimm32.
893-
def uimm32_coerced : Operand<i32> {
894-
let ParserMatchClass = !cast<AsmOperandClass>("UImm32CoercedAsmOperandClass");
895-
}
896867
// Like simm32 but coerces uimm32 to simm32.
897868
def simm32_relaxed : Operand<i32> {
898869
let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
@@ -2408,12 +2379,11 @@ def : MipsInstAlias<"sync",
24082379
// Assembler Pseudo Instructions
24092380
//===----------------------------------------------------------------------===//
24102381

2411-
// We use uimm32_coerced to accept a 33 bit signed number that is rendered into
2412-
// a 32 bit number.
2382+
// We use i32imm on li/la to defer range checking to the assembler.
24132383
class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
24142384
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
24152385
!strconcat(instr_asm, "\t$rt, $imm32")> ;
2416-
def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>;
2386+
def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>;
24172387

24182388
class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
24192389
RegisterOperand RO> :

‎lib/Target/Mips/MipsSchedule.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -270,15 +270,11 @@ def II_ORI : InstrItinClass;
270270
def II_POP : InstrItinClass;
271271
def II_RDHWR : InstrItinClass;
272272
def II_RESTORE : InstrItinClass;
273-
def II_RECIP_S : InstrItinClass;
274-
def II_RECIP_D : InstrItinClass;
275273
def II_RINT_S : InstrItinClass;
276274
def II_RINT_D : InstrItinClass;
277275
def II_ROTR : InstrItinClass;
278276
def II_ROTRV : InstrItinClass;
279277
def II_ROUND : InstrItinClass;
280-
def II_RSQRT_S : InstrItinClass;
281-
def II_RSQRT_D : InstrItinClass;
282278
def II_SAVE : InstrItinClass;
283279
def II_SC : InstrItinClass;
284280
def II_SCD : InstrItinClass;
@@ -611,10 +607,6 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
611607
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
612608
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
613609
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
614-
InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>,
615-
InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>,
616-
InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>,
617-
InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>,
618610
InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
619611
InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
620612
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,

‎lib/Target/Mips/MipsScheduleGeneric.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -440,10 +440,6 @@ def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>;
440440
def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>;
441441
def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>;
442442

443-
// rsqrt.[ds], recip.[ds]
444-
def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>;
445-
def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>;
446-
447443
// MIPSR6
448444
// ======
449445
//

‎lib/Target/Mips/MipsScheduleP5600.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -448,9 +448,6 @@ def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
448448
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
449449
def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
450450

451-
def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
452-
def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
453-
454451
// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
455452
// fsub.[wd]
456453
def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>;

‎test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,3 @@
195195
0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
196196
0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
197197
0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
198-
0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
199-
0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
200-
0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
201-
0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8

‎test/MC/Disassembler/Mips/micromips32r3/valid.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,3 @@
199199
0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
200200
0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
201201
0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
202-
0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
203-
0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
204-
0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
205-
0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8

‎test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,12 +135,8 @@
135135
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
136136
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
137137
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
138-
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
139-
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
140138
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
141139
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
142-
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
143-
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
144140
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
145141
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
146142
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)

‎test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -286,10 +286,6 @@
286286
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
287287
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
288288
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
289-
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
290-
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
291-
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
292-
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
293289
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
294290
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
295291
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12

‎test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,13 @@
7070
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
7171
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
7272
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
73+
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
74+
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
7375
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
7476
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
7577
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
78+
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
79+
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
7680
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
7781
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
7882
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31

‎test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -129,14 +129,10 @@
129129
0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
130130
0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
131131
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
132-
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
133-
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
134132
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
135133
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
136134
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
137135
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
138-
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
139-
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
140136
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
141137
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
142138
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)

‎test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -283,10 +283,6 @@
283283
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
284284
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
285285
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
286-
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
287-
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
288-
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
289-
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
290286
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
291287
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
292288
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12

‎test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,13 @@
7070
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
7171
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
7272
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
73+
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
74+
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
7375
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
7476
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
7577
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
78+
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
79+
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
7680
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
7781
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
7882
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31

‎test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -131,12 +131,8 @@
131131
0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
132132
0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
133133
0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
134-
0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
135-
0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
136134
0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
137135
0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
138-
0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
139-
0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
140136
0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
141137
0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
142138
0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)

‎test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -284,10 +284,6 @@
284284
0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
285285
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
286286
0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
287-
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
288-
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
289-
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
290-
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
291287
0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
292288
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
293289
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12

‎test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,13 @@
7070
0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
7171
0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
7272
0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
73+
0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
74+
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
7375
0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
7476
0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
7577
0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
78+
0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
79+
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
7680
0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
7781
0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
7882
0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31

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