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[mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]
Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265014 91177308-0d34-0410-b5e6-96231b3b80d8
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7 files changed

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‎lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1055,9 +1055,11 @@ class MipsOperand : public MCParsedAsmOperand {
10551055
bool isConstantMemOff() const {
10561056
return isMem() && isa<MCConstantExpr>(getMemOff());
10571057
}
1058-
template <unsigned Bits> bool isMemWithSimmOffset() const {
1059-
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
1060-
&& getMemBase()->isGPRAsmReg();
1058+
template <unsigned Bits, unsigned ShiftAmount = 0>
1059+
bool isMemWithSimmOffset() const {
1060+
return isMem() && isConstantMemOff() &&
1061+
isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()) &&
1062+
getMemBase()->isGPRAsmReg();
10611063
}
10621064
template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
10631065
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff()) &&
@@ -3800,6 +3802,18 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
38003802
case Match_MemGPSImm9:
38013803
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
38023804
"expected memory with $gp and 9-bit signed offset");
3805+
case Match_MemSImm10:
3806+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3807+
"expected memory with 10-bit signed offset");
3808+
case Match_MemSImm10Lsl1:
3809+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3810+
"expected memory with 11-bit signed offset and multiple of 2");
3811+
case Match_MemSImm10Lsl2:
3812+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3813+
"expected memory with 12-bit signed offset and multiple of 4");
3814+
case Match_MemSImm10Lsl3:
3815+
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3816+
"expected memory with 13-bit signed offset and multiple of 8");
38033817
}
38043818

38053819
llvm_unreachable("Implement any new match types added!");

‎lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Lines changed: 8 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -653,61 +653,20 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
653653
return getExprOpValue(MO.getExpr(),Fixups, STI);
654654
}
655655

656-
/// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
657-
/// instructions.
658-
unsigned
659-
MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
660-
SmallVectorImpl<MCFixup> &Fixups,
661-
const MCSubtargetInfo &STI) const {
662-
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
663-
assert(MI.getOperand(OpNo).isReg());
664-
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
665-
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
666-
667-
// The immediate field of an LD/ST instruction is scaled which means it must
668-
// be divided (when encoding) by the size (in bytes) of the instructions'
669-
// data format.
670-
// .b - 1 byte
671-
// .h - 2 bytes
672-
// .w - 4 bytes
673-
// .d - 8 bytes
674-
switch(MI.getOpcode())
675-
{
676-
default:
677-
assert (0 && "Unexpected instruction");
678-
break;
679-
case Mips::LD_B:
680-
case Mips::ST_B:
681-
// We don't need to scale the offset in this case
682-
break;
683-
case Mips::LD_H:
684-
case Mips::ST_H:
685-
OffBits >>= 1;
686-
break;
687-
case Mips::LD_W:
688-
case Mips::ST_W:
689-
OffBits >>= 2;
690-
break;
691-
case Mips::LD_D:
692-
case Mips::ST_D:
693-
OffBits >>= 3;
694-
break;
695-
}
696-
697-
return (OffBits & 0xFFFF) | RegBits;
698-
}
699-
700-
/// getMemEncoding - Return binary encoding of memory related operand.
656+
/// Return binary encoding of memory related operand.
701657
/// If the offset operand requires relocation, record the relocation.
702-
unsigned
703-
MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
704-
SmallVectorImpl<MCFixup> &Fixups,
705-
const MCSubtargetInfo &STI) const {
658+
template <unsigned ShiftAmount>
659+
unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
660+
SmallVectorImpl<MCFixup> &Fixups,
661+
const MCSubtargetInfo &STI) const {
706662
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
707663
assert(MI.getOperand(OpNo).isReg());
708664
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
709665
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
710666

667+
// Apply the scale factor if there is one.
668+
OffBits >>= ShiftAmount;
669+
711670
return (OffBits & 0xFFFF) | RegBits;
712671
}
713672

‎lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,7 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
161161
SmallVectorImpl<MCFixup> &Fixups,
162162
const MCSubtargetInfo &STI) const;
163163

164+
template <unsigned ShiftAmount = 0>
164165
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
165166
SmallVectorImpl<MCFixup> &Fixups,
166167
const MCSubtargetInfo &STI) const;

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 63 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -465,8 +465,29 @@ def UImm16RelaxedAsmOperandClass
465465
}
466466
def UImm16AsmOperandClass
467467
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
468+
def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
469+
let Name = "SImm10Lsl3";
470+
let RenderMethod = "addImmOperands";
471+
let PredicateMethod = "isScaledSImm<10, 3>";
472+
let SuperClasses = [UImm16AsmOperandClass];
473+
let DiagnosticType = "SImm10_Lsl3";
474+
}
475+
def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
476+
let Name = "SImm10Lsl2";
477+
let RenderMethod = "addImmOperands";
478+
let PredicateMethod = "isScaledSImm<10, 2>";
479+
let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];
480+
let DiagnosticType = "SImm10_Lsl2";
481+
}
482+
def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {
483+
let Name = "SImm10Lsl1";
484+
let RenderMethod = "addImmOperands";
485+
let PredicateMethod = "isScaledSImm<10, 1>";
486+
let SuperClasses = [ConstantSImm10Lsl2AsmOperandClass];
487+
let DiagnosticType = "SImm10_Lsl1";
488+
}
468489
def ConstantUImm10AsmOperandClass
469-
: ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>;
490+
: ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>;
470491
def ConstantSImm10AsmOperandClass
471492
: ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>;
472493
def ConstantSImm9AsmOperandClass
@@ -577,7 +598,6 @@ def calltarget : Operand<iPTR> {
577598

578599
def imm64: Operand<i64>;
579600

580-
def simm10 : Operand<i32>;
581601
def simm11 : Operand<i32>;
582602

583603
def simm16 : Operand<i32> {
@@ -743,13 +763,20 @@ foreach I = {1, 2, 3, 4, 5, 6, 8} in
743763
}
744764

745765
// Signed operands
746-
foreach I = {4, 5, 6, 9} in
766+
foreach I = {4, 5, 6, 9, 10} in
747767
def simm # I : Operand<i32> {
748768
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
749769
let ParserMatchClass =
750770
!cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");
751771
}
752772

773+
foreach I = {1, 2, 3} in
774+
def simm10_lsl # I : Operand<i32> {
775+
let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">";
776+
let ParserMatchClass =
777+
!cast<AsmOperandClass>("ConstantSImm10Lsl" # I # "AsmOperandClass");
778+
}
779+
753780
foreach I = {10} in
754781
def simm # I # _64 : Operand<i64> {
755782
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
@@ -793,6 +820,25 @@ def MipsMemSimm9AsmOperand : AsmOperandClass {
793820
let DiagnosticType = "MemSImm9";
794821
}
795822

823+
def MipsMemSimm10AsmOperand : AsmOperandClass {
824+
let Name = "MemOffsetSimm10";
825+
let SuperClasses = [MipsMemAsmOperand];
826+
let RenderMethod = "addMemOperands";
827+
let ParserMethod = "parseMemOperand";
828+
let PredicateMethod = "isMemWithSimmOffset<10>";
829+
let DiagnosticType = "MemSImm10";
830+
}
831+
832+
foreach I = {1, 2, 3} in
833+
def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass {
834+
let Name = "MemOffsetSimm10_" # I;
835+
let SuperClasses = [MipsMemAsmOperand];
836+
let RenderMethod = "addMemOperands";
837+
let ParserMethod = "parseMemOperand";
838+
let PredicateMethod = "isMemWithSimmOffset<10, " # I # ">";
839+
let DiagnosticType = "MemSImm10Lsl" # I;
840+
}
841+
796842
def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
797843
let Name = "MemOffsetSimm9GPR";
798844
let SuperClasses = [MipsMemAsmOperand];
@@ -855,6 +901,20 @@ def mem_simm9 : mem_generic {
855901
let ParserMatchClass = MipsMemSimm9AsmOperand;
856902
}
857903

904+
def mem_simm10 : mem_generic {
905+
let MIOperandInfo = (ops ptr_rc, simm10);
906+
let EncoderMethod = "getMemEncoding";
907+
let ParserMatchClass = MipsMemSimm10AsmOperand;
908+
}
909+
910+
foreach I = {1, 2, 3} in
911+
def mem_simm10_lsl # I : mem_generic {
912+
let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I));
913+
let EncoderMethod = "getMemEncoding<" # I # ">";
914+
let ParserMatchClass =
915+
!cast<AsmOperandClass>("MipsMemSimm10Lsl" # I # "AsmOperand");
916+
}
917+
858918
def mem_simm9gpr : mem_generic {
859919
let MIOperandInfo = (ops ptr_rc, simm9);
860920
let EncoderMethod = "getMemEncoding";

‎lib/Target/Mips/MipsMSAInstrInfo.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2297,7 +2297,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1
22972297

22982298
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
22992299
ValueType TyNode, RegisterOperand ROWD,
2300-
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2300+
Operand MemOpnd, ComplexPattern Addr = addrimm10,
23012301
InstrItinClass itin = NoItinerary> {
23022302
dag OutOperandList = (outs ROWD:$wd);
23032303
dag InOperandList = (ins MemOpnd:$addr);
@@ -2307,10 +2307,10 @@ class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
23072307
string DecoderMethod = "DecodeMSA128Mem";
23082308
}
23092309

2310-
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2311-
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2312-
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2313-
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2310+
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2311+
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
2312+
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
2313+
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
23142314

23152315
class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
23162316
class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
@@ -2631,7 +2631,7 @@ class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
26312631

26322632
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
26332633
ValueType TyNode, RegisterOperand ROWD,
2634-
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2634+
Operand MemOpnd, ComplexPattern Addr = addrimm10,
26352635
InstrItinClass itin = NoItinerary> {
26362636
dag OutOperandList = (outs);
26372637
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
@@ -2641,10 +2641,10 @@ class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
26412641
string DecoderMethod = "DecodeMSA128Mem";
26422642
}
26432643

2644-
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2645-
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2646-
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2647-
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2644+
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2645+
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
2646+
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
2647+
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
26482648

26492649
class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
26502650
MSA128BOpnd>;

‎test/MC/Mips/msa/invalid.s

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,14 @@
135135
insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
136136
insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
137137
insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'
138+
ld.b $w0, -513($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
139+
ld.b $w0, 512($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
140+
ld.h $w0, -1025($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
141+
ld.h $w0, 1024($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
142+
ld.w $w0, -2049($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
143+
ld.w $w0, 2048($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
144+
ld.d $w0, -4097($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
145+
ld.d $w0, 4096($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
138146
ldi.b $w1, -1025 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
139147
ldi.b $w1, 1024 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
140148
ldi.h $w1, -1025 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
@@ -259,6 +267,14 @@
259267
srlri.w $w18, $w3, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
260268
srlri.d $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
261269
srlri.d $w18, $w3, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
270+
st.b $w0, -513($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
271+
st.b $w0, 512($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
272+
st.h $w0, -1025($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
273+
st.h $w0, 1024($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
274+
st.w $w0, -2049($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
275+
st.w $w0, 2048($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
276+
st.d $w0, -4097($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
277+
st.d $w0, 4096($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
262278
subvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
263279
subvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
264280
subvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate

‎test/MC/Mips/msa/test_mi10.s

Lines changed: 23 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1,55 +1,28 @@
11
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
22
#
3-
# CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
4-
# CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
5-
# CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
3+
ld.b $w0, -512($1) # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
4+
ld.b $w1, 0($2) # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
5+
ld.b $w2, 511($3) # CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
66

7-
# CHECK: ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
8-
# CHECK: ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
9-
# CHECK: ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
10-
# CHECK: ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
11-
# CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
7+
ld.h $w3, -1024($4) # CHECK: ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
8+
ld.h $w4, -512($5) # CHECK: ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
9+
ld.h $w5, 0($6) # CHECK: ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
10+
ld.h $w6, 512($7) # CHECK: ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
11+
ld.h $w7, 1022($8) # CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
1212

13-
# CHECK: ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
14-
# CHECK: ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
15-
# CHECK: ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
16-
# CHECK: ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
17-
# CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
18-
# CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
13+
ld.w $w8, -2048($9) # CHECK: ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
14+
ld.w $w9, -1024($10) # CHECK: ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
15+
ld.w $w10, -512($11) # CHECK: ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
16+
ld.w $w11, 512($12) # CHECK: ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
17+
ld.w $w12, 1024($13) # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
18+
ld.w $w13, 2044($14) # CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
1919

20-
# CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
21-
# CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
22-
# CHECK: ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
23-
# CHECK: ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
24-
# CHECK: ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
25-
# CHECK: ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
26-
# CHECK: ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
27-
# CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
28-
# CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]
29-
30-
ld.b $w0, -512($1)
31-
ld.b $w1, 0($2)
32-
ld.b $w2, 511($3)
33-
34-
ld.h $w3, -1024($4)
35-
ld.h $w4, -512($5)
36-
ld.h $w5, 0($6)
37-
ld.h $w6, 512($7)
38-
ld.h $w7, 1022($8)
39-
40-
ld.w $w8, -2048($9)
41-
ld.w $w9, -1024($10)
42-
ld.w $w10, -512($11)
43-
ld.w $w11, 512($12)
44-
ld.w $w12, 1024($13)
45-
ld.w $w13, 2044($14)
46-
47-
ld.d $w14, -4096($15)
48-
ld.d $w15, -2048($16)
49-
ld.d $w16, -1024($17)
50-
ld.d $w17, -512($18)
51-
ld.d $w18, 0($19)
52-
ld.d $w19, 512($20)
53-
ld.d $w20, 1024($21)
54-
ld.d $w21, 2048($22)
55-
ld.d $w22, 4088($23)
20+
ld.d $w14, -4096($15) # CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
21+
ld.d $w15, -2048($16) # CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
22+
ld.d $w16, -1024($17) # CHECK: ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
23+
ld.d $w17, -512($18) # CHECK: ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
24+
ld.d $w18, 0($19) # CHECK: ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
25+
ld.d $w19, 512($20) # CHECK: ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
26+
ld.d $w20, 1024($21) # CHECK: ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
27+
ld.d $w21, 2048($22) # CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
28+
ld.d $w22, 4088($23) # CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]

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