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Commit 359c877

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EugeneZelenkoEugeneZelenko
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[AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289475 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 2229ea1 commit 359c877

11 files changed

+206
-145
lines changed

‎lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -13,14 +13,10 @@
1313
//===----------------------------------------------------------------------===//
1414

1515
#include "AMDGPUSubtarget.h"
16-
#include "R600ISelLowering.h"
17-
#include "R600InstrInfo.h"
18-
#include "SIFrameLowering.h"
19-
#include "SIISelLowering.h"
20-
#include "SIInstrInfo.h"
21-
#include "SIMachineFunctionInfo.h"
2216
#include "llvm/ADT/SmallString.h"
2317
#include "llvm/CodeGen/MachineScheduler.h"
18+
#include "llvm/Target/TargetFrameLowering.h"
19+
#include <algorithm>
2420

2521
using namespace llvm;
2622

@@ -31,7 +27,7 @@ using namespace llvm;
3127
#define GET_SUBTARGETINFO_CTOR
3228
#include "AMDGPUGenSubtargetInfo.inc"
3329

34-
AMDGPUSubtarget::~AMDGPUSubtarget() {}
30+
AMDGPUSubtarget::~AMDGPUSubtarget() = default;
3531

3632
AMDGPUSubtarget &
3733
AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
@@ -124,8 +120,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
124120
ScalarizeGlobal(false),
125121

126122
FeatureDisable(false),
127-
InstrItins(getInstrItineraryForCPU(GPU)),
128-
TSInfo() {
123+
InstrItins(getInstrItineraryForCPU(GPU)) {
129124
initializeSubtargetDependencies(TT, GPU, FS);
130125
}
131126

@@ -189,7 +184,6 @@ unsigned AMDGPUSubtarget::getOccupancyWithLocalMemSize(uint32_t Bytes) const {
189184

190185
std::pair<unsigned, unsigned> AMDGPUSubtarget::getFlatWorkGroupSizes(
191186
const Function &F) const {
192-
193187
// Default minimum/maximum flat work group sizes.
194188
std::pair<unsigned, unsigned> Default =
195189
AMDGPU::isCompute(F.getCallingConv()) ?
@@ -222,7 +216,6 @@ std::pair<unsigned, unsigned> AMDGPUSubtarget::getFlatWorkGroupSizes(
222216

223217
std::pair<unsigned, unsigned> AMDGPUSubtarget::getWavesPerEU(
224218
const Function &F) const {
225-
226219
// Default minimum/maximum number of waves per execution unit.
227220
std::pair<unsigned, unsigned> Default(1, 0);
228221

@@ -281,8 +274,7 @@ SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
281274
AMDGPUSubtarget(TT, GPU, FS, TM),
282275
InstrInfo(*this),
283276
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
284-
TLInfo(TM, *this),
285-
GISel() {}
277+
TLInfo(TM, *this) {}
286278

287279
void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
288280
unsigned NumRegionInstrs) const {

‎lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 26 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -19,13 +19,15 @@
1919
#include "AMDGPUTargetObjectFile.h"
2020
#include "AMDGPUTargetTransformInfo.h"
2121
#include "GCNSchedStrategy.h"
22-
#include "R600ISelLowering.h"
23-
#include "R600InstrInfo.h"
2422
#include "R600MachineScheduler.h"
25-
#include "SIISelLowering.h"
26-
#include "SIInstrInfo.h"
2723
#include "SIMachineScheduler.h"
24+
#include "llvm/ADT/SmallString.h"
25+
#include "llvm/ADT/STLExtras.h"
26+
#include "llvm/ADT/StringRef.h"
27+
#include "llvm/ADT/Triple.h"
28+
#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
2829
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30+
#include "llvm/CodeGen/MachineScheduler.h"
2931
#include "llvm/CodeGen/Passes.h"
3032
#include "llvm/CodeGen/TargetPassConfig.h"
3133
#include "llvm/Support/TargetRegistry.h"
@@ -34,7 +36,14 @@
3436
#include "llvm/Transforms/Scalar.h"
3537
#include "llvm/Transforms/Scalar/GVN.h"
3638
#include "llvm/Transforms/Vectorize.h"
39+
#include "llvm/IR/Attributes.h"
40+
#include "llvm/IR/Function.h"
3741
#include "llvm/IR/LegacyPassManager.h"
42+
#include "llvm/Pass.h"
43+
#include "llvm/Support/CommandLine.h"
44+
#include "llvm/Support/Compiler.h"
45+
#include "llvm/Target/TargetLoweringObjectFile.h"
46+
#include <memory>
3847

3948
using namespace llvm;
4049

@@ -69,7 +78,6 @@ static cl::opt<bool> ScalarizeGlobal(
6978
cl::init(false),
7079
cl::Hidden);
7180

72-
7381
extern "C" void LLVMInitializeAMDGPUTarget() {
7482
// Register the target
7583
RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
@@ -97,11 +105,11 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
97105
}
98106

99107
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100-
return make_unique<AMDGPUTargetObjectFile>();
108+
return llvm::make_unique<AMDGPUTargetObjectFile>();
101109
}
102110

103111
static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
104-
return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
112+
return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
105113
}
106114

107115
static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
@@ -111,7 +119,8 @@ static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
111119
static ScheduleDAGInstrs *
112120
createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
113121
ScheduleDAGMILive *DAG =
114-
new ScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
122+
new ScheduleDAGMILive(C,
123+
llvm::make_unique<GCNMaxOccupancySchedStrategy>(C));
115124
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
116125
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
117126
return DAG;
@@ -170,12 +179,11 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
170179
CodeGenOpt::Level OptLevel)
171180
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
172181
FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
173-
TLOF(createTLOF(getTargetTriple())),
174-
IntrinsicInfo() {
182+
TLOF(createTLOF(getTargetTriple())) {
175183
initAsmInfo();
176184
}
177185

178-
AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
186+
AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
179187

180188
StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
181189
Attribute GPUAttr = F.getFnAttribute("target-cpu");
@@ -192,7 +200,7 @@ StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
192200
}
193201

194202
void AMDGPUTargetMachine::addEarlyAsPossiblePasses(PassManagerBase &PM) {
195-
PM.add(llvm::createAMDGPUUnifyMetadataPass());
203+
PM.add(createAMDGPUUnifyMetadataPass());
196204
}
197205

198206
//===----------------------------------------------------------------------===//
@@ -234,13 +242,15 @@ const R600Subtarget *R600TargetMachine::getSubtargetImpl(
234242

235243
#ifdef LLVM_BUILD_GLOBAL_ISEL
236244
namespace {
245+
237246
struct SIGISelActualAccessor : public GISelAccessor {
238247
std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
239248
const AMDGPUCallLowering *getCallLowering() const override {
240249
return CallLoweringInfo.get();
241250
}
242251
};
243-
} // End anonymous namespace.
252+
253+
} // end anonymous namespace
244254
#endif
245255

246256
GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
@@ -291,7 +301,6 @@ class AMDGPUPassConfig : public TargetPassConfig {
291301
public:
292302
AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
293303
: TargetPassConfig(TM, PM) {
294-
295304
// Exceptions and StackMaps are not supported, so these passes will never do
296305
// anything.
297306
disablePass(&StackMapLivenessID);
@@ -322,7 +331,7 @@ class AMDGPUPassConfig : public TargetPassConfig {
322331
class R600PassConfig final : public AMDGPUPassConfig {
323332
public:
324333
R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
325-
: AMDGPUPassConfig(TM, PM) { }
334+
: AMDGPUPassConfig(TM, PM) {}
326335

327336
ScheduleDAGInstrs *createMachineScheduler(
328337
MachineSchedContext *C) const override {
@@ -338,7 +347,7 @@ class R600PassConfig final : public AMDGPUPassConfig {
338347
class GCNPassConfig final : public AMDGPUPassConfig {
339348
public:
340349
GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
341-
: AMDGPUPassConfig(TM, PM) { }
350+
: AMDGPUPassConfig(TM, PM) {}
342351

343352
GCNTargetMachine &getGCNTargetMachine() const {
344353
return getTM<GCNTargetMachine>();
@@ -365,7 +374,7 @@ class GCNPassConfig final : public AMDGPUPassConfig {
365374
void addPreEmitPass() override;
366375
};
367376

368-
} // End of anonymous namespace
377+
} // end anonymous namespace
369378

370379
TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
371380
return TargetIRAnalysis([this](const Function &F) {

‎lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,14 @@
1515
#include "Utils/AMDGPUBaseInfo.h"
1616
#include "llvm/MC/MCExpr.h"
1717
#include "llvm/MC/MCInst.h"
18+
#include "llvm/MC/MCInstrDesc.h"
1819
#include "llvm/MC/MCInstrInfo.h"
1920
#include "llvm/MC/MCRegisterInfo.h"
2021
#include "llvm/MC/MCSubtargetInfo.h"
22+
#include "llvm/Support/ErrorHandling.h"
2123
#include "llvm/Support/MathExtras.h"
2224
#include "llvm/Support/raw_ostream.h"
23-
24-
#include <string>
25+
#include <cassert>
2526

2627
using namespace llvm;
2728
using namespace llvm::AMDGPU;
@@ -450,7 +451,6 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
450451
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
451452
const MCSubtargetInfo &STI,
452453
raw_ostream &O) {
453-
454454
if (OpNo >= MI->getNumOperands()) {
455455
O << "/*Missing OP" << OpNo << "*/";
456456
return;
@@ -940,7 +940,6 @@ void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
940940
default:
941941
break;
942942
}
943-
return;
944943
}
945944

946945
void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
@@ -1037,7 +1036,7 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
10371036
O << "sendmsg(" << IdSymbolic[Id] << ", " << OpSysSymbolic[OpSys] << ')';
10381037
return;
10391038
}
1040-
} while (0);
1039+
} while (false);
10411040
O << SImm16; // Unknown simm16 code.
10421041
}
10431042

‎lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,25 +20,30 @@
2020
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
2121
#include "llvm/MC/MCCodeEmitter.h"
2222
#include "llvm/MC/MCContext.h"
23+
#include "llvm/MC/MCFixup.h"
2324
#include "llvm/MC/MCInst.h"
25+
#include "llvm/MC/MCInstrDesc.h"
2426
#include "llvm/MC/MCInstrInfo.h"
2527
#include "llvm/MC/MCRegisterInfo.h"
2628
#include "llvm/MC/MCSubtargetInfo.h"
29+
#include "llvm/Support/Endian.h"
2730
#include "llvm/Support/EndianStream.h"
2831
#include "llvm/Support/raw_ostream.h"
32+
#include <cassert>
33+
#include <cstdint>
2934

3035
using namespace llvm;
3136

3237
namespace {
3338

3439
class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
35-
R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
36-
void operator=(const R600MCCodeEmitter &) = delete;
3740
const MCRegisterInfo &MRI;
3841

3942
public:
4043
R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
41-
: AMDGPUMCCodeEmitter(mcii), MRI(mri) { }
44+
: AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
45+
R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
46+
R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
4247

4348
/// \brief Encode the instruction and write it to the OS.
4449
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
@@ -57,7 +62,7 @@ class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
5762
unsigned getHWReg(unsigned regNo) const;
5863
};
5964

60-
} // End anonymous namespace
65+
} // end anonymous namespace
6166

6267
enum RegElement {
6368
ELEMENT_X = 0,

‎lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -------------------------------===//
1+
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
22
//
33
// The LLVM Compiler Infrastructure
44
//
@@ -17,25 +17,30 @@
1717
#include "MCTargetDesc/AMDGPUFixupKinds.h"
1818
#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
1919
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20-
#include "SIDefines.h"
2120
#include "Utils/AMDGPUBaseInfo.h"
2221
#include "llvm/MC/MCCodeEmitter.h"
2322
#include "llvm/MC/MCContext.h"
23+
#include "llvm/MC/MCExpr.h"
2424
#include "llvm/MC/MCFixup.h"
2525
#include "llvm/MC/MCInst.h"
26+
#include "llvm/MC/MCInstrDesc.h"
2627
#include "llvm/MC/MCInstrInfo.h"
2728
#include "llvm/MC/MCRegisterInfo.h"
2829
#include "llvm/MC/MCSubtargetInfo.h"
2930
#include "llvm/MC/MCSymbol.h"
31+
#include "llvm/Support/Casting.h"
32+
#include "llvm/Support/ErrorHandling.h"
33+
#include "llvm/Support/MathExtras.h"
3034
#include "llvm/Support/raw_ostream.h"
35+
#include <cassert>
36+
#include <cstdint>
37+
#include <cstdlib>
3138

3239
using namespace llvm;
3340

3441
namespace {
3542

3643
class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
37-
SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
38-
void operator=(const SIMCCodeEmitter &) = delete;
3944
const MCRegisterInfo &MRI;
4045

4146
/// \brief Encode an fp or int literal
@@ -46,8 +51,8 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
4651
SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
4752
MCContext &ctx)
4853
: AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
49-
50-
~SIMCCodeEmitter() override {}
54+
SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
55+
SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
5156

5257
/// \brief Encode the instruction and write it to the OS.
5358
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
@@ -66,7 +71,7 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
6671
const MCSubtargetInfo &STI) const override;
6772
};
6873

69-
} // End anonymous namespace
74+
} // end anonymous namespace
7075

7176
MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
7277
const MCRegisterInfo &MRI,
@@ -198,10 +203,9 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
198203
uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
199204
const MCOperandInfo &OpInfo,
200205
const MCSubtargetInfo &STI) const {
201-
202206
int64_t Imm;
203207
if (MO.isExpr()) {
204-
const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr());
208+
const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
205209
if (!C)
206210
return 255;
207211

@@ -263,7 +267,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
263267
if (Op.isImm())
264268
Imm = Op.getImm();
265269
else if (Op.isExpr()) {
266-
if (const MCConstantExpr *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
270+
if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
267271
Imm = C->getValue();
268272

269273
} else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
@@ -301,7 +305,7 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
301305
return MRI.getEncodingValue(MO.getReg());
302306

303307
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
304-
const MCSymbolRefExpr *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
308+
const auto *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
305309
MCFixupKind Kind;
306310
if (Expr && Expr->getSymbol().isExternal())
307311
Kind = FK_Data_4;
@@ -329,4 +333,3 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
329333
llvm_unreachable("Encoding of this operand type is not supported yet.");
330334
return 0;
331335
}
332-

‎lib/Target/AMDGPU/R600FrameLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,5 +11,4 @@
1111

1212
using namespace llvm;
1313

14-
R600FrameLowering::~R600FrameLowering() {
15-
}
14+
R600FrameLowering::~R600FrameLowering() = default;

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