Skip to content
This repository was archived by the owner on Mar 28, 2020. It is now read-only.

Commit 45cd9c2

Browse files
arsenmarsenm
committed
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374284 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 9590c44 commit 45cd9c2

File tree

52 files changed

+356
-352
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

52 files changed

+356
-352
lines changed

‎lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -643,7 +643,7 @@ static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
643643
case 3:
644644
return AMDGPU::SGPR_96RegClassID;
645645
case 4:
646-
return AMDGPU::SReg_128RegClassID;
646+
return AMDGPU::SGPR_128RegClassID;
647647
case 5:
648648
return AMDGPU::SGPR_160RegClassID;
649649
case 8:
@@ -783,7 +783,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
783783
SDValue RC, SubReg0, SubReg1;
784784
SDLoc DL(N);
785785
if (N->getValueType(0) == MVT::i128) {
786-
RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
786+
RC = CurDAG->getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32);
787787
SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
788788
SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
789789
} else if (N->getValueType(0) == MVT::i64) {

‎lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,7 +1052,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
10521052
return true;
10531053

10541054
if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1055-
!AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {
1055+
!AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
10561056
return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
10571057
}
10581058

@@ -1101,7 +1101,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
11011101

11021102
if (YamlMFI.ArgInfo &&
11031103
(parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1104-
AMDGPU::SReg_128RegClass,
1104+
AMDGPU::SGPR_128RegClass,
11051105
MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
11061106
parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
11071107
AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,

‎lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
125125
addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
126126
addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
127127

128-
addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
129-
addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
128+
addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
129+
addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
130130

131-
addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
131+
addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
132132
addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
133133

134134
addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
@@ -10494,7 +10494,7 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
1049410494

1049510495
// Combine the constants and the pointer.
1049610496
const SDValue Ops1[] = {
10497-
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
10497+
DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
1049810498
Ptr,
1049910499
DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
1050010500
SubRegHi,
@@ -10524,7 +10524,7 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
1052410524
SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
1052510525

1052610526
const SDValue Ops[] = {
10527-
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
10527+
DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
1052810528
PtrLo,
1052910529
DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1053010530
PtrHi,
@@ -10567,7 +10567,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1056710567
RC = &AMDGPU::SReg_96RegClass;
1056810568
break;
1056910569
case 128:
10570-
RC = &AMDGPU::SReg_128RegClass;
10570+
RC = &AMDGPU::SGPR_128RegClass;
1057110571
break;
1057210572
case 160:
1057310573
RC = &AMDGPU::SReg_160RegClass;

‎lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4267,7 +4267,7 @@ emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
42674267
Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
42684268
Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
42694269
Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4270-
Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
4270+
Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
42714271

42724272
// Beginning of the loop, read the next Rsrc variant.
42734273
BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
@@ -4406,7 +4406,7 @@ extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
44064406
Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
44074407
Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
44084408
Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4409-
Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
4409+
Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
44104410
uint64_t RsrcDataFormat = TII.getDefaultRsrcDataFormat();
44114411

44124412
// Zero64 = 0
@@ -6178,7 +6178,7 @@ bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
61786178
return false;
61796179

61806180
const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
6181-
return RCID == AMDGPU::SReg_128RegClassID;
6181+
return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
61826182
}
61836183

61846184
bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,

‎lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1120,7 +1120,7 @@ SILoadStoreOptimizer::getTargetRegisterClass(const CombineInfo &CI) {
11201120
case 2:
11211121
return &AMDGPU::SReg_64_XEXECRegClass;
11221122
case 4:
1123-
return &AMDGPU::SReg_128RegClass;
1123+
return &AMDGPU::SGPR_128RegClass;
11241124
case 8:
11251125
return &AMDGPU::SReg_256RegClass;
11261126
case 16:

‎lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
189189
const SIRegisterInfo &TRI) {
190190
ArgInfo.PrivateSegmentBuffer =
191191
ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
192-
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
192+
getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
193193
NumUserSGPRs += 4;
194194
return ArgInfo.PrivateSegmentBuffer.getRegister();
195195
}

‎lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
123123
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
124124
unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
125125
unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
126-
return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
126+
return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
127127
}
128128

129129
static unsigned findPrivateSegmentWaveByteOffsetRegIndex(unsigned RegCount) {
@@ -1546,7 +1546,7 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
15461546
case 96:
15471547
return &AMDGPU::SReg_96RegClass;
15481548
case 128:
1549-
return &AMDGPU::SReg_128RegClass;
1549+
return &AMDGPU::SGPR_128RegClass;
15501550
case 160:
15511551
return &AMDGPU::SReg_160RegClass;
15521552
case 256:
@@ -1576,7 +1576,7 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
15761576
case 3:
15771577
return &AMDGPU::SReg_96RegClass;
15781578
case 4:
1579-
return &AMDGPU::SReg_128RegClass;
1579+
return &AMDGPU::SGPR_128RegClass;
15801580
case 5:
15811581
return &AMDGPU::SReg_160RegClass;
15821582
case 8:
@@ -1966,7 +1966,7 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
19661966
&AMDGPU::SReg_96RegClass;
19671967
case 128:
19681968
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass :
1969-
&AMDGPU::SReg_128RegClass;
1969+
&AMDGPU::SGPR_128RegClass;
19701970
case 160:
19711971
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass :
19721972
&AMDGPU::SReg_160RegClass;
@@ -1990,9 +1990,12 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
19901990
const TargetRegisterClass *
19911991
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
19921992
const MachineRegisterInfo &MRI) const {
1993-
if (const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg()))
1993+
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
1994+
if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
19941995
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
1995-
return nullptr;
1996+
1997+
const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>();
1998+
return getAllocatableClass(RC);
19961999
}
19972000

19982001
unsigned SIRegisterInfo::getVCC() const {

‎lib/Target/AMDGPU/SIRegisterInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -529,6 +529,7 @@ def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
529529
def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
530530
(add SGPR_128, TTMP_128)> {
531531
let AllocationPriority = 15;
532+
let isAllocatable = 0;
532533
}
533534

534535
} // End CopyCost = 2

‎test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ body: |
143143
; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
144144
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
145145
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
146-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
146+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
147147
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
148148
%0:sgpr(s64) = COPY $sgpr0_sgpr1
149149
%1:sgpr(s64) = COPY $sgpr2_sgpr3

‎test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ body: |
146146
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
147147
; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
148148
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
149-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
149+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
150150
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
151151
%0:sgpr(<2 x s16>) = COPY $sgpr0
152152
%1:sgpr(<2 x s16>) = COPY $sgpr1
@@ -192,7 +192,7 @@ body: |
192192
; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v4s16_s_v4s16
193193
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
194194
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
195-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
195+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
196196
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
197197
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
198198
%1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
@@ -350,8 +350,8 @@ body: |
350350
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
351351
352352
; GCN-LABEL: name: test_concat_vectors_s_v12s16_s_v8s16_s_v8s16
353-
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
354-
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
353+
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
354+
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
355355
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
356356
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
357357
%0:sgpr(<8 x s16>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -461,7 +461,7 @@ body: |
461461
; GCN-LABEL: name: test_concat_vectors_s_v4s32_s_v2s32_s_v2s32
462462
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
463463
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
464-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
464+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
465465
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
466466
%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
467467
%1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
@@ -524,8 +524,8 @@ body: |
524524
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
525525
526526
; GCN-LABEL: name: test_concat_vectors_s_v8s32_s_v4s32_s_v4s32
527-
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
528-
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
527+
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
528+
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
529529
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
530530
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
531531
%0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -596,8 +596,8 @@ body: |
596596
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
597597
598598
; GCN-LABEL: name: test_concat_vectors_s_v4s64_s_v2s64_s_v2s64
599-
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
600-
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
599+
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
600+
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
601601
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
602602
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
603603
%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -656,10 +656,10 @@ body: |
656656
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12_sgpr13_sgpr14_sgpr15
657657
658658
; GCN-LABEL: name: test_concat_vectors_s_v8s64_s_v2s64_s_v2s64_s_v2s64_s_v2s64
659-
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
660-
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
661-
; GCN: [[COPY2:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
662-
; GCN: [[COPY3:%[0-9]+]]:sreg_128 = COPY $sgpr12_sgpr13_sgpr14_sgpr15
659+
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
660+
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
661+
; GCN: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
662+
; GCN: [[COPY3:%[0-9]+]]:sgpr_128 = COPY $sgpr12_sgpr13_sgpr14_sgpr15
663663
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7, [[COPY2]], %subreg.sub8_sub9_sub10_sub11, [[COPY3]], %subreg.sub12_sub13_sub14_sub15
664664
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
665665
%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -680,8 +680,8 @@ body: |
680680
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
681681
682682
; GCN-LABEL: name: test_concat_vectors_s_v4p1_s_v2p1_s_v2p1
683-
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
684-
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
683+
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
684+
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
685685
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
686686
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
687687
%0:sgpr(<2 x p1>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
@@ -702,7 +702,7 @@ body: |
702702
; GCN-LABEL: name: test_concat_vectors_s_v4p3_s_v2p3_s_v2p3
703703
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
704704
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
705-
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
705+
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
706706
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
707707
%0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
708708
%1:sgpr(<2 x p3>) = COPY $sgpr2_sgpr3

‎test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -256,9 +256,9 @@ body: |
256256
bb.0:
257257
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
258258
; CHECK-LABEL: name: insert_s_s128_s_s64_0
259-
; CHECK: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
259+
; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
260260
; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
261-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
261+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
262262
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
263263
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
264264
%1:sgpr(s64) = COPY $sgpr4_sgpr5
@@ -291,9 +291,9 @@ body: |
291291
bb.0:
292292
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
293293
; CHECK-LABEL: name: insert_s_s128_s_s64_64
294-
; CHECK: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
294+
; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
295295
; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
296-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
296+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
297297
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
298298
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
299299
%1:sgpr(s64) = COPY $sgpr4_sgpr5
@@ -368,7 +368,7 @@ body: |
368368
; CHECK-LABEL: name: insert_s_s128_s_s96_0
369369
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
370370
; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
371-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
371+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
372372
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
373373
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
374374
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
@@ -388,7 +388,7 @@ body: |
388388
; CHECK-LABEL: name: insert_s_s128_s_s96_32
389389
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
390390
; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
391-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
391+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
392392
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
393393
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
394394
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
@@ -468,7 +468,7 @@ body: |
468468
469469
; CHECK-LABEL: name: insert_s_s256_s_s128_0
470470
; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
471-
; CHECK: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
471+
; CHECK: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
472472
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
473473
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
474474
%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7

0 commit comments

Comments
 (0)