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Commit 47eb9d5

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getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281498 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent fb1804b commit 47eb9d5

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3 files changed

+6
-8
lines changed

3 files changed

+6
-8
lines changed

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1216,7 +1216,7 @@ SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
12161216
}
12171217

12181218
// Add the offset to the index.
1219-
unsigned EltSize = Vec.getValueType().getScalarSizeInBits() / 8;
1219+
unsigned EltSize = Vec.getScalarValueSizeInBits() / 8;
12201220
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
12211221
DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
12221222

@@ -1267,7 +1267,7 @@ SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
12671267
// Then store the inserted part.
12681268

12691269
// Add the offset to the index.
1270-
unsigned EltSize = Vec.getValueType().getScalarSizeInBits() / 8;
1270+
unsigned EltSize = Vec.getScalarValueSizeInBits() / 8;
12711271

12721272
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
12731273
DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));

lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -794,8 +794,7 @@ void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
794794
// Note that in some cases vector operation operands may be greater than
795795
// the vector element type. For example BUILD_VECTOR of type <1 x i1> with
796796
// a constant i8 operand.
797-
assert(Result.getValueSizeInBits() >=
798-
Op.getValueType().getScalarSizeInBits() &&
797+
assert(Result.getValueSizeInBits() >= Op.getScalarValueSizeInBits() &&
799798
"Invalid type for scalarized vector");
800799
AnalyzeNewValue(Result);
801800

@@ -913,7 +912,7 @@ SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
913912
/// Convert to a vector of integers of the same size.
914913
SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) {
915914
assert(Op.getValueType().isVector() && "Only applies to vectors!");
916-
unsigned EltWidth = Op.getValueType().getScalarSizeInBits();
915+
unsigned EltWidth = Op.getScalarValueSizeInBits();
917916
EVT EltNVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
918917
unsigned NumElts = Op.getValueType().getVectorNumElements();
919918
return DAG.getNode(ISD::BITCAST, SDLoc(Op),

lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6698,8 +6698,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
66986698
return SDValue();
66996699

67006700
SDValue Vec = Op.getOperand(0);
6701-
if (Op.getValueType() == MVT::i32 &&
6702-
Vec.getValueType().getScalarSizeInBits() < 32) {
6701+
if (Op.getValueType() == MVT::i32 && Vec.getScalarValueSizeInBits() < 32) {
67036702
SDLoc dl(Op);
67046703
return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
67056704
}
@@ -10516,7 +10515,7 @@ static SDValue PerformVDUPLANECombine(SDNode *N,
1051610515
return SDValue();
1051710516

1051810517
// Make sure the VMOV element size is not bigger than the VDUPLANE elements.
10519-
unsigned EltSize = Op.getValueType().getScalarSizeInBits();
10518+
unsigned EltSize = Op.getScalarValueSizeInBits();
1052010519
// The canonical VMOV for a zero vector uses a 32-bit element size.
1052110520
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1052210521
unsigned EltBits;

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