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[InstSimplify] Add tests for signed icmp of and/or; NFC
Even if a signed predicate is used, the ranges computed for and/or are unsigned, resulting in missed simplifications. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356720 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/Transforms/InstSimplify/icmp-constant.ll

Lines changed: 150 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,95 @@ define <2 x i1> @or1_vec(<2 x i32> %X) {
378378
ret <2 x i1> %B
379379
}
380380

381+
; Single bit OR.
382+
define i1 @or2_true(i8 %x) {
383+
; CHECK-LABEL: @or2_true(
384+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], 64
385+
; CHECK-NEXT: [[Z:%.*]] = icmp sge i8 [[Y]], -64
386+
; CHECK-NEXT: ret i1 [[Z]]
387+
;
388+
%y = or i8 %x, 64
389+
%z = icmp sge i8 %y, -64
390+
ret i1 %z
391+
}
392+
393+
define i1 @or2_unknown(i8 %x) {
394+
; CHECK-LABEL: @or2_unknown(
395+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], 64
396+
; CHECK-NEXT: [[Z:%.*]] = icmp sgt i8 [[Y]], -64
397+
; CHECK-NEXT: ret i1 [[Z]]
398+
;
399+
%y = or i8 %x, 64
400+
%z = icmp sgt i8 %y, -64
401+
ret i1 %z
402+
}
403+
404+
; Multi bit OR.
405+
; 78 = 0b01001110; -50 = 0b11001110
406+
define i1 @or3_true(i8 %x) {
407+
; CHECK-LABEL: @or3_true(
408+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], 78
409+
; CHECK-NEXT: [[Z:%.*]] = icmp sge i8 [[Y]], -50
410+
; CHECK-NEXT: ret i1 [[Z]]
411+
;
412+
%y = or i8 %x, 78
413+
%z = icmp sge i8 %y, -50
414+
ret i1 %z
415+
}
416+
417+
define i1 @or3_unknown(i8 %x) {
418+
; CHECK-LABEL: @or3_unknown(
419+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], 78
420+
; CHECK-NEXT: [[Z:%.*]] = icmp sgt i8 [[Y]], -50
421+
; CHECK-NEXT: ret i1 [[Z]]
422+
;
423+
%y = or i8 %x, 78
424+
%z = icmp sgt i8 %y, -50
425+
ret i1 %z
426+
}
427+
428+
; OR with sign bit.
429+
define i1 @or4_true(i8 %x) {
430+
; CHECK-LABEL: @or4_true(
431+
; CHECK-NEXT: ret i1 true
432+
;
433+
%y = or i8 %x, -64
434+
%z = icmp sge i8 %y, -64
435+
ret i1 %z
436+
}
437+
438+
define i1 @or4_unknown(i8 %x) {
439+
; CHECK-LABEL: @or4_unknown(
440+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], -64
441+
; CHECK-NEXT: [[Z:%.*]] = icmp sgt i8 [[Y]], -64
442+
; CHECK-NEXT: ret i1 [[Z]]
443+
;
444+
%y = or i8 %x, -64
445+
%z = icmp sgt i8 %y, -64
446+
ret i1 %z
447+
}
448+
449+
; If sign bit is set, signed & unsigned ranges are the same.
450+
define i1 @or5_true(i8 %x) {
451+
; CHECK-LABEL: @or5_true(
452+
; CHECK-NEXT: ret i1 true
453+
;
454+
%y = or i8 %x, -64
455+
%z = icmp uge i8 %y, -64
456+
ret i1 %z
457+
}
458+
459+
define i1 @or5_unknown(i8 %x) {
460+
; CHECK-LABEL: @or5_unknown(
461+
; CHECK-NEXT: [[Y:%.*]] = or i8 [[X:%.*]], -64
462+
; CHECK-NEXT: [[Z:%.*]] = icmp ugt i8 [[Y]], -64
463+
; CHECK-NEXT: ret i1 [[Z]]
464+
;
465+
%y = or i8 %x, -64
466+
%z = icmp ugt i8 %y, -64
467+
ret i1 %z
468+
}
469+
381470
; 'and x, C2' produces [0, C2]
382471
define i1 @and1(i32 %X) {
383472
; CHECK-LABEL: @and1(
@@ -397,6 +486,61 @@ define <2 x i1> @and1_vec(<2 x i32> %X) {
397486
ret <2 x i1> %B
398487
}
399488

489+
; If the sign bit is not set, signed and unsigned ranges are the same.
490+
define i1 @and2(i32 %X) {
491+
; CHECK-LABEL: @and2(
492+
; CHECK-NEXT: ret i1 false
493+
;
494+
%A = and i32 %X, 62
495+
%B = icmp sgt i32 %A, 70
496+
ret i1 %B
497+
}
498+
499+
; -75 = 0b10110101, 53 = 0b00110101
500+
define i1 @and3_true1(i8 %x) {
501+
; CHECK-LABEL: @and3_true1(
502+
; CHECK-NEXT: [[Y:%.*]] = and i8 [[X:%.*]], -75
503+
; CHECK-NEXT: [[Z:%.*]] = icmp sge i8 [[Y]], -75
504+
; CHECK-NEXT: ret i1 [[Z]]
505+
;
506+
%y = and i8 %x, -75
507+
%z = icmp sge i8 %y, -75
508+
ret i1 %z
509+
}
510+
511+
define i1 @and3_unknown1(i8 %x) {
512+
; CHECK-LABEL: @and3_unknown1(
513+
; CHECK-NEXT: [[Y:%.*]] = and i8 [[X:%.*]], -75
514+
; CHECK-NEXT: [[Z:%.*]] = icmp sgt i8 [[Y]], -75
515+
; CHECK-NEXT: ret i1 [[Z]]
516+
;
517+
%y = and i8 %x, -75
518+
%z = icmp sgt i8 %y, -75
519+
ret i1 %z
520+
}
521+
522+
define i1 @and3_true2(i8 %x) {
523+
; CHECK-LABEL: @and3_true2(
524+
; CHECK-NEXT: [[Y:%.*]] = and i8 [[X:%.*]], -75
525+
; CHECK-NEXT: [[Z:%.*]] = icmp sle i8 [[Y]], 53
526+
; CHECK-NEXT: ret i1 [[Z]]
527+
;
528+
%y = and i8 %x, -75
529+
%z = icmp sle i8 %y, 53
530+
ret i1 %z
531+
}
532+
533+
define i1 @and3_unknown2(i8 %x) {
534+
; CHECK-LABEL: @and3_unknown2(
535+
; CHECK-NEXT: [[Y:%.*]] = and i8 [[X:%.*]], -75
536+
; CHECK-NEXT: [[Z:%.*]] = icmp slt i8 [[Y]], 53
537+
; CHECK-NEXT: ret i1 [[Z]]
538+
;
539+
%y = and i8 %x, -75
540+
%z = icmp slt i8 %y, 53
541+
ret i1 %z
542+
}
543+
400544
; 'add nuw x, C2' produces [C2, UINT_MAX]
401545
define i1 @tautological9(i32 %x) {
402546
; CHECK-LABEL: @tautological9(
@@ -431,7 +575,7 @@ define i1 @add_nsw_neg_const1(i32 %x) {
431575

432576
define i1 @add_nsw_neg_const2(i32 %x) {
433577
; CHECK-LABEL: @add_nsw_neg_const2(
434-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, -2147483647
578+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], -2147483647
435579
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[ADD]], -1
436580
; CHECK-NEXT: ret i1 [[CMP]]
437581
;
@@ -455,7 +599,7 @@ define i1 @add_nsw_neg_const3(i32 %x) {
455599

456600
define i1 @add_nsw_neg_const4(i32 %x) {
457601
; CHECK-LABEL: @add_nsw_neg_const4(
458-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, -2147483646
602+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], -2147483646
459603
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[ADD]], 0
460604
; CHECK-NEXT: ret i1 [[CMP]]
461605
;
@@ -479,7 +623,7 @@ define i1 @add_nsw_neg_const5(i32 %x) {
479623

480624
define i1 @add_nsw_neg_const6(i32 %x) {
481625
; CHECK-LABEL: @add_nsw_neg_const6(
482-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, -42
626+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], -42
483627
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[ADD]], 2147483605
484628
; CHECK-NEXT: ret i1 [[CMP]]
485629
;
@@ -503,7 +647,7 @@ define i1 @add_nsw_pos_const1(i32 %x) {
503647

504648
define i1 @add_nsw_pos_const2(i32 %x) {
505649
; CHECK-LABEL: @add_nsw_pos_const2(
506-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, 2147483647
650+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], 2147483647
507651
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD]], 0
508652
; CHECK-NEXT: ret i1 [[CMP]]
509653
;
@@ -527,7 +671,7 @@ define i1 @add_nsw_pos_const3(i32 %x) {
527671

528672
define i1 @add_nsw_pos_const4(i32 %x) {
529673
; CHECK-LABEL: @add_nsw_pos_const4(
530-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, 2147483646
674+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], 2147483646
531675
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD]], -1
532676
; CHECK-NEXT: ret i1 [[CMP]]
533677
;
@@ -551,7 +695,7 @@ define i1 @add_nsw_pos_const5(i32 %x) {
551695

552696
define i1 @add_nsw_pos_const6(i32 %x) {
553697
; CHECK-LABEL: @add_nsw_pos_const6(
554-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 %x, 42
698+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[X:%.*]], 42
555699
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ADD]], -2147483606
556700
; CHECK-NEXT: ret i1 [[CMP]]
557701
;

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