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JonPssonJonPsson
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[SystemZ] Increase the number of VLREPs
If a loaded value is replicated it is best to combine these two operations into a VLREP (load and replicate), but isel will not produce this if the load has other users as well. This patch handles this by putting the other users of the load to use the REPLICATE 0-element instead of the load. This way the load has only the REPLICATE node as user, and we get a VLREP. Review: Ulrich Weigand https://reviews.llvm.org/D54264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346746 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/SystemZ/SystemZISelLowering.cpp

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@@ -523,6 +523,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
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setTargetDAGCombine(ISD::LOAD);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
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setTargetDAGCombine(ISD::FP_ROUND);
@@ -5368,6 +5369,46 @@ SDValue SystemZTargetLowering::combineMERGE(
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return SDValue();
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}
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SDValue SystemZTargetLowering::combineLOAD(
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SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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EVT LdVT = N->getValueType(0);
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if (LdVT.isVector() || LdVT.isInteger())
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return SDValue();
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// Transform a scalar load that is REPLICATEd as well as having other
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// use(s) to the form where the other use(s) use the first element of the
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// REPLICATE instead of the load. Otherwise instruction selection will not
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// produce a VLREP. Avoid extracting to a GPR, so only do this for floating
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// point loads.
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SDValue Replicate;
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SmallVector<SDNode*, 8> OtherUses;
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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UI != UE; ++UI) {
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if (UI->getOpcode() == SystemZISD::REPLICATE) {
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if (Replicate)
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return SDValue(); // Should never happen
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Replicate = SDValue(*UI, 0);
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}
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else if (UI.getUse().getResNo() == 0)
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OtherUses.push_back(*UI);
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}
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if (!Replicate || OtherUses.empty())
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return SDValue();
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SDLoc DL(N);
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SDValue Extract0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, LdVT,
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Replicate, DAG.getConstant(0, DL, MVT::i32));
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// Update uses of the loaded Value while preserving old chains.
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for (SDNode *U : OtherUses) {
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SmallVector<SDValue, 8> Ops;
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for (SDValue Op : U->ops())
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Ops.push_back((Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op);
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DAG.UpdateNodeOperands(U, Ops);
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}
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return SDValue(N, 0);
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}
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SDValue SystemZTargetLowering::combineSTORE(
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SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
@@ -5699,6 +5740,7 @@ SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SIGN_EXTEND_INREG: return combineSIGN_EXTEND_INREG(N, DCI);
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case SystemZISD::MERGE_HIGH:
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case SystemZISD::MERGE_LOW: return combineMERGE(N, DCI);
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case ISD::LOAD: return combineLOAD(N, DCI);
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case ISD::STORE: return combineSTORE(N, DCI);
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case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
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case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);

‎lib/Target/SystemZ/SystemZISelLowering.h

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@@ -587,6 +587,7 @@ class SystemZTargetLowering : public TargetLowering {
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SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;

‎test/CodeGen/SystemZ/vec-move-21.ll

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@@ -0,0 +1,56 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test that a replicate of a load gets folded to vlrep also in cases where
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; the load has multiple users.
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; CHECK-NOT: vrep
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define double @fun(double* %Vsrc, <2 x double> %T) {
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entry:
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%Vgep1 = getelementptr double, double* %Vsrc, i64 0
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%Vld1 = load double, double* %Vgep1
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%Vgep2 = getelementptr double, double* %Vsrc, i64 1
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%Vld2 = load double, double* %Vgep2
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%Vgep3 = getelementptr double, double* %Vsrc, i64 2
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%Vld3 = load double, double* %Vgep3
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%Vgep4 = getelementptr double, double* %Vsrc, i64 3
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%Vld4 = load double, double* %Vgep4
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%Vgep5 = getelementptr double, double* %Vsrc, i64 4
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%Vld5 = load double, double* %Vgep5
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%Vgep6 = getelementptr double, double* %Vsrc, i64 5
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%Vld6 = load double, double* %Vgep6
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%V19 = insertelement <2 x double> undef, double %Vld1, i32 0
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%V20 = shufflevector <2 x double> %V19, <2 x double> undef, <2 x i32> zeroinitializer
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%V21 = insertelement <2 x double> undef, double %Vld4, i32 0
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%V22 = insertelement <2 x double> %V21, double %Vld5, i32 1
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%V23 = fmul <2 x double> %V20, %V22
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%V24 = fadd <2 x double> %T, %V23
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%V25 = insertelement <2 x double> %V19, double %Vld2, i32 1
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%V26 = insertelement <2 x double> undef, double %Vld6, i32 0
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%V27 = insertelement <2 x double> %V26, double %Vld6, i32 1
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%V28 = fmul <2 x double> %V25, %V27
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%V29 = fadd <2 x double> %T, %V28
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%V30 = insertelement <2 x double> undef, double %Vld2, i32 0
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%V31 = shufflevector <2 x double> %V30, <2 x double> undef, <2 x i32> zeroinitializer
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%V32 = insertelement <2 x double> undef, double %Vld5, i32 0
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%V33 = insertelement <2 x double> %V32, double %Vld6, i32 1
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%V34 = fmul <2 x double> %V31, %V33
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%V35 = fadd <2 x double> %T, %V34
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%V36 = insertelement <2 x double> undef, double %Vld3, i32 0
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%V37 = shufflevector <2 x double> %V36, <2 x double> undef, <2 x i32> zeroinitializer
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%V38 = fmul <2 x double> %V37, %V22
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%V39 = fadd <2 x double> %T, %V38
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%Vmul37 = fmul double %Vld3, %Vld6
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%Vadd38 = fadd double %Vmul37, %Vmul37
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%VA0 = fadd <2 x double> %V24, %V29
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%VA1 = fadd <2 x double> %VA0, %V35
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%VA2 = fadd <2 x double> %VA1, %V39
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%VE0 = extractelement <2 x double> %VA2, i32 0
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%VS1 = fadd double %VE0, %Vadd38
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ret double %VS1
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}

‎test/CodeGen/SystemZ/vec-move-22.ll

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@@ -0,0 +1,15 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test that a loaded value which is used both in a vector and scalar context
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; is not transformed to a vlrep + vlgvg.
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; CHECK-NOT: vlrep
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define void @fun(i64 %arg, i64** %Addr, <2 x i64*>* %Dst) {
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%tmp10 = load i64*, i64** %Addr
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store i64 %arg, i64* %tmp10
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%tmp12 = insertelement <2 x i64*> undef, i64* %tmp10, i32 0
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%tmp13 = insertelement <2 x i64*> %tmp12, i64* %tmp10, i32 1
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store <2 x i64*> %tmp13, <2 x i64*>* %Dst
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ret void
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}

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