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[AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands
See bug 39332: https://bugs.llvm.org/show_bug.cgi?id=39332 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D56794 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351555 91177308-0d34-0410-b5e6-96231b3b80d8
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‎docs/AMDGPUOperandSyntax.rst

Lines changed: 16 additions & 16 deletions
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@@ -523,22 +523,22 @@ Floating-point *inline constants* are converted to
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:ref:`expected operand type<amdgpu_syn_instruction_type>`
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as described :ref:`here<amdgpu_synid_fp_const_conv>`.
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================================== ===================================================== ==================
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Value Note Availability
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================================== ===================================================== ==================
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0.0 The same as integer constant 0. All GPUs
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0.5 Floating-point constant 0.5 All GPUs
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1.0 Floating-point constant 1.0 All GPUs
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2.0 Floating-point constant 2.0 All GPUs
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4.0 Floating-point constant 4.0 All GPUs
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-0.5 Floating-point constant -0.5 All GPUs
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-1.0 Floating-point constant -1.0 All GPUs
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-2.0 Floating-point constant -2.0 All GPUs
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-4.0 Floating-point constant -4.0 All GPUs
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0.1592 1.0/(2.0*pi). Use only for 16-bit operands. GFX8, GFX9
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0.15915494 1.0/(2.0*pi). Use only for 16- and 32-bit operands. GFX8, GFX9
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0.159154943091895317852646485335 1.0/(2.0*pi). GFX8, GFX9
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================================== ===================================================== ==================
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===================== ===================================================== ==================
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Value Note Availability
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===================== ===================================================== ==================
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0.0 The same as integer constant 0. All GPUs
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0.5 Floating-point constant 0.5 All GPUs
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1.0 Floating-point constant 1.0 All GPUs
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2.0 Floating-point constant 2.0 All GPUs
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4.0 Floating-point constant 4.0 All GPUs
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-0.5 Floating-point constant -0.5 All GPUs
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-1.0 Floating-point constant -1.0 All GPUs
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-2.0 Floating-point constant -2.0 All GPUs
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-4.0 Floating-point constant -4.0 All GPUs
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0.1592 1.0/(2.0*pi). Use only for 16-bit operands. GFX8, GFX9
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0.15915494 1.0/(2.0*pi). Use only for 16- and 32-bit operands. GFX8, GFX9
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0.15915494309189532 1.0/(2.0*pi). GFX8, GFX9
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===================== ===================================================== ==================
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.. WARNING:: GFX7 does not support inline constants for *f16* operands.
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‎lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -491,7 +491,7 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
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O << "-4.0";
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else if (Imm == 0x3fc45f306dc9c882 &&
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STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
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O << "0.15915494";
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O << "0.15915494309189532";
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else {
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assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
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‎test/CodeGen/AMDGPU/imm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -449,7 +449,7 @@ define amdgpu_kernel void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out,
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; SI: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
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; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x4c
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; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494{{$}}
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; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494309189532{{$}}
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; VI: buffer_store_dwordx2 [[REG]]
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define amdgpu_kernel void @add_inline_imm_inv_2pi_f64(double addrspace(1)* %out, [8 x i32], double %x) {
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%y = fadd double %x, 0x3fc45f306dc9c882

‎test/MC/AMDGPU/literals.s

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Original file line numberDiff line numberDiff line change
@@ -429,7 +429,7 @@ v_and_b32_e32 v0, 0xffffffffffffffff, v1
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v_trunc_f32_e32 v0, 0x3fc45f306dc9c882
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// NOSICI: error: invalid operand for instruction
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// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
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// VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
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v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882
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// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
@@ -445,7 +445,7 @@ v_fract_f64_e32 v[0:1], 0x3e22f983
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v_trunc_f32_e64 v0, 0x3fc45f306dc9c882
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// NOSICI: error: invalid operand for instruction
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// VI: v_fract_f64_e64 v[0:1], 0.15915494 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
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// VI: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
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v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882
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// NOSICI: error: invalid operand for instruction
@@ -457,7 +457,7 @@ v_trunc_f32_e64 v0, 0x3e22f983
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v_fract_f64_e64 v[0:1], 0x3e22f983
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// NOSICI: error: invalid operand for instruction
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// VI: s_mov_b64 s[0:1], 0.15915494 ; encoding: [0xf8,0x01,0x80,0xbe]
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// VI: s_mov_b64 s[0:1], 0.15915494309189532 ; encoding: [0xf8,0x01,0x80,0xbe]
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s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335
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// SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e]
@@ -469,7 +469,7 @@ v_and_b32_e32 v0, 0.159154943091895317852646485335, v1
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v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
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// SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f]
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// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
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// VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
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v_fract_f64 v[0:1], 0.159154943091895317852646485335
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// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]

‎test/MC/Disassembler/AMDGPU/literal_vi.txt

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@@ -0,0 +1,7 @@
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# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
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# VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
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0xf8,0x64,0x00,0x7e
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# VI: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e]
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0xf8,0x38,0x00,0x7e

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