[InstCombine] minimize tests and autogenerate checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278960 91177308-0d34-0410-b5e6-96231b3b80d8

Author: rotateright

test/Transforms/InstCombine/vec_sext.ll

@@ -1,45 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
-entry:
+define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @psignd_3(
+; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
+; CHECK-NEXT:    [[T1:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT:    [[T2:%.*]] = and <4 x i32> %a, [[T1]]
+; CHECK-NEXT:    [[T3:%.*]] = and <4 x i32> [[B_LOBIT]], [[SUB]]
+; CHECK-NEXT:    [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
+; CHECK-NEXT:    ret <4 x i32> [[COND]]
+;
   %cmp = icmp slt <4 x i32> %b, zeroinitializer
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
-  %0 = icmp slt <4 x i32> %sext, zeroinitializer
-  %sext3 = sext <4 x i1> %0 to <4 x i32>
-  %1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
-  %2 = and <4 x i32> %a, %1
-  %3 = and <4 x i32> %sext3, %sub
-  %cond = or <4 x i32> %2, %3
+  %t0 = icmp slt <4 x i32> %sext, zeroinitializer
+  %sext3 = sext <4 x i1> %t0 to <4 x i32>
+  %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %t2 = and <4 x i32> %a, %t1
+  %t3 = and <4 x i32> %sext3, %sub
+  %cond = or <4 x i32> %t2, %t3
   ret <4 x i32> %cond
-
-; CHECK-LABEL: @psignd_3
-; CHECK:   ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
-; CHECK:   sub nsw <4 x i32> zeroinitializer, %a
-; CHECK:   xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK:   and <4 x i32> %a, %0
-; CHECK:   and <4 x i32> %b.lobit, %sub
-; CHECK:   or <4 x i32> %1, %2
 }
 
-define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
-entry:
+define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    [[B_LOBIT_NOT:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
+; CHECK-NEXT:    [[T2:%.*]] = and <4 x i32> [[B_LOBIT]], %a
+; CHECK-NEXT:    [[T3:%.*]] = and <4 x i32> [[B_LOBIT_NOT]], [[SUB]]
+; CHECK-NEXT:    [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
+; CHECK-NEXT:    ret <4 x i32> [[COND]]
+;
   %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
-  %0 = icmp slt <4 x i32> %sext, zeroinitializer
-  %sext3 = sext <4 x i1> %0 to <4 x i32>
-  %1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
-  %2 = and <4 x i32> %a, %1
-  %3 = and <4 x i32> %sext3, %sub
-  %cond = or <4 x i32> %2, %3
+  %t0 = icmp slt <4 x i32> %sext, zeroinitializer
+  %sext3 = sext <4 x i1> %t0 to <4 x i32>
+  %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %t2 = and <4 x i32> %a, %t1
+  %t3 = and <4 x i32> %sext3, %sub
+  %cond = or <4 x i32> %t2, %t3
   ret <4 x i32> %cond
-
-; CHECK-LABEL: @test1
-; CHECK:   ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
-; CHECK:   xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK:   sub nsw <4 x i32> zeroinitializer, %a
-; CHECK:   and <4 x i32> %b.lobit, %a
-; CHECK:   and <4 x i32> %b.lobit.not, %sub
-; CHECK:   or <4 x i32> %0, %1
 }
+