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Alexander Ivchenkoaemerson
Alexander Ivchenko
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aemerson
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[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
This is logical continuation of https://reviews.llvm.org/D46018 (r332449) Differential Revision: https://reviews.llvm.org/D49660 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338685 91177308-0d34-0410-b5e6-96231b3b80d8 (cherry picked from commit 8c575a1)
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16 files changed

+425
-128
lines changed

16 files changed

+425
-128
lines changed

‎include/llvm/CodeGen/GlobalISel/CallLowering.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -138,12 +138,12 @@ class CallLowering {
138138
virtual ~CallLowering() = default;
139139

140140
/// This hook must be implemented to lower outgoing return values, described
141-
/// by \p Val, into the specified virtual register \p VReg.
141+
/// by \p Val, into the specified virtual registers \p VRegs.
142142
/// This hook is used by GlobalISel.
143143
///
144144
/// \return True if the lowering succeeds, false otherwise.
145-
virtual bool lowerReturn(MachineIRBuilder &MIRBuilder,
146-
const Value *Val, unsigned VReg) const {
145+
virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
146+
ArrayRef<unsigned> VRegs) const {
147147
return false;
148148
}
149149

‎lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -323,14 +323,16 @@ bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
323323
const Value *Ret = RI.getReturnValue();
324324
if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
325325
Ret = nullptr;
326+
327+
ArrayRef<unsigned> VRegs;
328+
if (Ret)
329+
VRegs = getOrCreateVRegs(*Ret);
330+
326331
// The target may mess up with the insertion point, but
327332
// this is not important as a return is the last instruction
328333
// of the block anyway.
329334

330-
// FIXME: this interface should simplify when CallLowering gets adapted to
331-
// multiple VRegs per Value.
332-
unsigned VReg = Ret ? packRegs(*Ret, MIRBuilder) : 0;
333-
return CLI->lowerReturn(MIRBuilder, Ret, VReg);
335+
return CLI->lowerReturn(MIRBuilder, Ret, VRegs);
334336
}
335337

336338
bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {

‎lib/Target/AArch64/AArch64CallLowering.cpp

Lines changed: 30 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -227,32 +227,45 @@ void AArch64CallLowering::splitToValueTypes(
227227
}
228228

229229
bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
230-
const Value *Val, unsigned VReg) const {
231-
MachineFunction &MF = MIRBuilder.getMF();
232-
const Function &F = MF.getFunction();
233-
230+
const Value *Val,
231+
ArrayRef<unsigned> VRegs) const {
234232
auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
235-
assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
236-
bool Success = true;
237-
if (VReg) {
238-
MachineRegisterInfo &MRI = MF.getRegInfo();
233+
assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
234+
"Return value without a vreg");
239235

240-
// We zero-extend i1s to i8.
241-
if (MRI.getType(VReg).getSizeInBits() == 1)
242-
VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg();
236+
bool Success = true;
237+
if (!VRegs.empty()) {
238+
MachineFunction &MF = MIRBuilder.getMF();
239+
const Function &F = MF.getFunction();
243240

241+
MachineRegisterInfo &MRI = MF.getRegInfo();
244242
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
245243
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
246244
auto &DL = F.getParent()->getDataLayout();
245+
LLVMContext &Ctx = Val->getType()->getContext();
247246

248-
ArgInfo OrigArg{VReg, Val->getType()};
249-
setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
247+
SmallVector<EVT, 4> SplitEVTs;
248+
ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
249+
assert(VRegs.size() == SplitEVTs.size() &&
250+
"For each split Type there should be exactly one VReg.");
250251

251252
SmallVector<ArgInfo, 8> SplitArgs;
252-
splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
253-
[&](unsigned Reg, uint64_t Offset) {
254-
MIRBuilder.buildExtract(Reg, VReg, Offset);
255-
});
253+
for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
254+
// We zero-extend i1s to i8.
255+
unsigned CurVReg = VRegs[i];
256+
if (MRI.getType(VRegs[i]).getSizeInBits() == 1) {
257+
CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg)
258+
->getOperand(0)
259+
.getReg();
260+
}
261+
262+
ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
263+
setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
264+
splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI, F.getCallingConv(),
265+
[&](unsigned Reg, uint64_t Offset) {
266+
MIRBuilder.buildExtract(Reg, CurVReg, Offset);
267+
});
268+
}
256269

257270
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
258271
Success = handleAssignments(MIRBuilder, SplitArgs, Handler);

‎lib/Target/AArch64/AArch64CallLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@ class AArch64CallLowering: public CallLowering {
3434
public:
3535
AArch64CallLowering(const AArch64TargetLowering &TLI);
3636

37-
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
38-
unsigned VReg) const override;
37+
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
38+
ArrayRef<unsigned> VRegs) const override;
3939

4040
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
4141
ArrayRef<unsigned> VRegs) const override;

‎lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
3232
}
3333

3434
bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
35-
const Value *Val, unsigned VReg) const {
35+
const Value *Val,
36+
ArrayRef<unsigned> VRegs) const {
3637
// FIXME: Add support for non-void returns.
3738
if (Val)
3839
return false;

‎lib/Target/AMDGPU/AMDGPUCallLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ class AMDGPUCallLowering: public CallLowering {
3535
public:
3636
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
3737

38-
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
39-
unsigned VReg) const override;
38+
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
39+
ArrayRef<unsigned> VRegs) const override;
4040
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
4141
ArrayRef<unsigned> VRegs) const override;
4242
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);

‎lib/Target/ARM/ARMCallLowering.cpp

Lines changed: 22 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,7 @@ void ARMCallLowering::splitToValueTypes(
237237
/// Lower the return value for the already existing \p Ret. This assumes that
238238
/// \p MIRBuilder's insertion point is correct.
239239
bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
240-
const Value *Val, unsigned VReg,
240+
const Value *Val, ArrayRef<unsigned> VRegs,
241241
MachineInstrBuilder &Ret) const {
242242
if (!Val)
243243
// Nothing to do here.
@@ -251,16 +251,24 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
251251
if (!isSupportedType(DL, TLI, Val->getType()))
252252
return false;
253253

254-
SmallVector<ArgInfo, 4> SplitVTs;
255-
SmallVector<unsigned, 4> Regs;
256-
ArgInfo RetInfo(VReg, Val->getType());
257-
setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);
258-
splitToValueTypes(RetInfo, SplitVTs, MF, [&](unsigned Reg, uint64_t Offset) {
259-
Regs.push_back(Reg);
260-
});
254+
SmallVector<EVT, 4> SplitEVTs;
255+
ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
256+
assert(VRegs.size() == SplitEVTs.size() &&
257+
"For each split Type there should be exactly one VReg.");
261258

262-
if (Regs.size() > 1)
263-
MIRBuilder.buildUnmerge(Regs, VReg);
259+
SmallVector<ArgInfo, 4> SplitVTs;
260+
LLVMContext &Ctx = Val->getType()->getContext();
261+
for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
262+
ArgInfo CurArgInfo(VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx));
263+
setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
264+
265+
SmallVector<unsigned, 4> Regs;
266+
splitToValueTypes(
267+
CurArgInfo, SplitVTs, MF,
268+
[&](unsigned Reg, uint64_t Offset) { Regs.push_back(Reg); });
269+
if (Regs.size() > 1)
270+
MIRBuilder.buildUnmerge(Regs, VRegs[i]);
271+
}
264272

265273
CCAssignFn *AssignFn =
266274
TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
@@ -270,14 +278,15 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
270278
}
271279

272280
bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
273-
const Value *Val, unsigned VReg) const {
274-
assert(!Val == !VReg && "Return value without a vreg");
281+
const Value *Val,
282+
ArrayRef<unsigned> VRegs) const {
283+
assert(!Val == VRegs.empty() && "Return value without a vreg");
275284

276285
auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
277286
unsigned Opcode = ST.getReturnOpcode();
278287
auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
279288

280-
if (!lowerReturnVal(MIRBuilder, Val, VReg, Ret))
289+
if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
281290
return false;
282291

283292
MIRBuilder.insertInstr(Ret);

‎lib/Target/ARM/ARMCallLowering.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ class ARMCallLowering : public CallLowering {
3333
public:
3434
ARMCallLowering(const ARMTargetLowering &TLI);
3535

36-
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
37-
unsigned VReg) const override;
36+
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
37+
ArrayRef<unsigned> VRegs) const override;
3838

3939
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
4040
ArrayRef<unsigned> VRegs) const override;
@@ -45,7 +45,8 @@ class ARMCallLowering : public CallLowering {
4545

4646
private:
4747
bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
48-
unsigned VReg, MachineInstrBuilder &Ret) const;
48+
ArrayRef<unsigned> VRegs,
49+
MachineInstrBuilder &Ret) const;
4950

5051
using SplitArgTy = std::function<void(unsigned Reg, uint64_t Offset)>;
5152

‎lib/Target/Mips/MipsCallLowering.cpp

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "MipsCallLowering.h"
1717
#include "MipsCCState.h"
1818
#include "MipsTargetMachine.h"
19+
#include "llvm/CodeGen/Analysis.h"
1920
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2021

2122
using namespace llvm;
@@ -190,25 +191,34 @@ static bool isSupportedType(Type *T) {
190191
}
191192

192193
bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
193-
const Value *Val, unsigned VReg) const {
194+
const Value *Val,
195+
ArrayRef<unsigned> VRegs) const {
194196

195197
MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
196198

197-
if (Val != nullptr) {
198-
if (!isSupportedType(Val->getType()))
199-
return false;
199+
if (Val != nullptr && !isSupportedType(Val->getType()))
200+
return false;
200201

202+
if (!VRegs.empty()) {
201203
MachineFunction &MF = MIRBuilder.getMF();
202204
const Function &F = MF.getFunction();
203205
const DataLayout &DL = MF.getDataLayout();
204206
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
207+
LLVMContext &Ctx = Val->getType()->getContext();
208+
209+
SmallVector<EVT, 4> SplitEVTs;
210+
ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
211+
assert(VRegs.size() == SplitEVTs.size() &&
212+
"For each split Type there should be exactly one VReg.");
205213

206214
SmallVector<ArgInfo, 8> RetInfos;
207215
SmallVector<unsigned, 8> OrigArgIndices;
208216

209-
ArgInfo ArgRetInfo(VReg, Val->getType());
210-
setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
211-
splitToValueTypes(ArgRetInfo, 0, RetInfos, OrigArgIndices);
217+
for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
218+
ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
219+
setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
220+
splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
221+
}
212222

213223
SmallVector<ISD::OutputArg, 8> Outs;
214224
subTargetRegTypeForCallingConv(

‎lib/Target/Mips/MipsCallLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ class MipsCallLowering : public CallLowering {
5050

5151
MipsCallLowering(const MipsTargetLowering &TLI);
5252

53-
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
54-
unsigned VReg) const override;
53+
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
54+
ArrayRef<unsigned> VRegs) const;
5555

5656
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
5757
ArrayRef<unsigned> VRegs) const override;

‎lib/Target/X86/X86CallLowering.cpp

Lines changed: 24 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -65,10 +65,8 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
6565
SmallVector<uint64_t, 4> Offsets;
6666
ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
6767

68-
if (SplitVTs.size() != 1) {
69-
// TODO: support struct/array split
70-
return false;
71-
}
68+
if (OrigArg.Ty->isVoidTy())
69+
return true;
7270

7371
EVT VT = SplitVTs[0];
7472
unsigned NumParts = TLI.getNumRegisters(Context, VT);
@@ -185,27 +183,36 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
185183

186184
} // end anonymous namespace
187185

188-
bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
189-
const Value *Val, unsigned VReg) const {
190-
assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
191-
186+
bool X86CallLowering::lowerReturn(
187+
MachineIRBuilder &MIRBuilder, const Value *Val,
188+
ArrayRef<unsigned> VRegs) const {
189+
assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
190+
"Return value without a vreg");
192191
auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
193192

194-
if (VReg) {
193+
if (!VRegs.empty()) {
195194
MachineFunction &MF = MIRBuilder.getMF();
195+
const Function &F = MF.getFunction();
196196
MachineRegisterInfo &MRI = MF.getRegInfo();
197197
auto &DL = MF.getDataLayout();
198-
const Function &F = MF.getFunction();
198+
LLVMContext &Ctx = Val->getType()->getContext();
199+
const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
199200

200-
ArgInfo OrigArg{VReg, Val->getType()};
201-
setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
201+
SmallVector<EVT, 4> SplitEVTs;
202+
ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
203+
assert(VRegs.size() == SplitEVTs.size() &&
204+
"For each split Type there should be exactly one VReg.");
202205

203206
SmallVector<ArgInfo, 8> SplitArgs;
204-
if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
205-
[&](ArrayRef<unsigned> Regs) {
206-
MIRBuilder.buildUnmerge(Regs, VReg);
207-
}))
208-
return false;
207+
for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
208+
ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
209+
setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
210+
if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
211+
[&](ArrayRef<unsigned> Regs) {
212+
MIRBuilder.buildUnmerge(Regs, VRegs[i]);
213+
}))
214+
return false;
215+
}
209216

210217
OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
211218
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))

‎lib/Target/X86/X86CallLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@ class X86CallLowering : public CallLowering {
2929
public:
3030
X86CallLowering(const X86TargetLowering &TLI);
3131

32-
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
33-
unsigned VReg) const override;
32+
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
33+
ArrayRef<unsigned> VRegs) const override;
3434

3535
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
3636
ArrayRef<unsigned> VRegs) const override;

‎test/CodeGen/AArch64/GlobalISel/call-translator.ll

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -97,18 +97,10 @@ define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr)
9797
; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
9898
; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[ADDR]], [[CST2]](s64)
9999
; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.addr + 16, align 8)
100-
; CHECK: [[IMPDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
101-
; CHECK: [[INS1:%[0-9]+]]:_(s192) = G_INSERT [[IMPDEF]], [[LD1]](s64), 0
102-
; CHECK: [[INS2:%[0-9]+]]:_(s192) = G_INSERT [[INS1]], [[LD2]](s64), 64
103-
; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_INSERT [[INS2]], [[LD3]](s32), 128
104100

105-
; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
106-
; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
107-
; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
108-
109-
; CHECK: $d0 = COPY [[DBL]](s64)
110-
; CHECK: $x0 = COPY [[I64]](s64)
111-
; CHECK: $w1 = COPY [[I32]](s32)
101+
; CHECK: $d0 = COPY [[LD1]](s64)
102+
; CHECK: $x0 = COPY [[LD2]](s64)
103+
; CHECK: $w1 = COPY [[LD3]](s32)
112104
; CHECK: RET_ReallyLR implicit $d0, implicit $x0, implicit $w1
113105
define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
114106
%val = load {double, i64, i32}, {double, i64, i32}* %addr

‎test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -19,20 +19,15 @@ declare i32 @llvm.eh.typeid.for(i8*)
1919

2020
; CHECK: [[BAD]].{{[a-z]+}} (landing-pad):
2121
; CHECK: EH_LABEL
22-
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY $x0
22+
; CHECK: [[PTR_RET:%[0-9]+]]:_(p0) = COPY $x0
2323
; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY $x1
24-
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
25-
; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
26-
; CHECK: [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
27-
; CHECK: [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
28-
; CHECK: [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
29-
; CHECK: [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
24+
; CHECK: [[SEL_RET:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
3025
; CHECK: $x0 = COPY [[PTR_RET]]
3126
; CHECK: $w1 = COPY [[SEL_RET]]
3227

3328
; CHECK: [[GOOD]].{{[a-z]+}}:
3429
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
35-
; CHECK: {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
30+
; CHECK: $w1 = COPY [[SEL]]
3631

3732
define { i8*, i32 } @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
3833
%res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken

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