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[Power9] Builtins for ELF v.2 API conformance - back end portion
This patch corresponds to review: https://reviews.llvm.org/D24396 This patch adds support for the "vector count trailing zeroes", "vector compare not equal" and "vector compare not equal or zero instructions" as well as "scalar count trailing zeroes" instructions. It also changes the vector negation to use XXLNOR (when VSX is enabled) so as not to increase register pressure (previously this was done with a splat immediate of all ones followed by an XXLXOR). This was done because the altivec.h builtins (patch to follow) use vector negation and the use of an additional register for the splat immediate is not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282478 91177308-0d34-0410-b5e6-96231b3b80d8
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‎include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
250250
def int_ppc_altivec_vcmpgtuw : GCCBuiltin<"__builtin_altivec_vcmpgtuw">,
251251
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
252252
[IntrNoMem]>;
253+
def int_ppc_altivec_vcmpnew : GCCBuiltin<"__builtin_altivec_vcmpnew">,
254+
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
255+
[IntrNoMem]>;
256+
def int_ppc_altivec_vcmpnezw : GCCBuiltin<"__builtin_altivec_vcmpnezw">,
257+
Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
258+
[IntrNoMem]>;
253259

254260
def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">,
255261
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
@@ -260,6 +266,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
260266
def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">,
261267
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
262268
[IntrNoMem]>;
269+
def int_ppc_altivec_vcmpneh : GCCBuiltin<"__builtin_altivec_vcmpneh">,
270+
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
271+
[IntrNoMem]>;
272+
def int_ppc_altivec_vcmpnezh : GCCBuiltin<"__builtin_altivec_vcmpnezh">,
273+
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
274+
[IntrNoMem]>;
263275

264276
def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">,
265277
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
@@ -270,6 +282,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
270282
def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">,
271283
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
272284
[IntrNoMem]>;
285+
def int_ppc_altivec_vcmpneb : GCCBuiltin<"__builtin_altivec_vcmpneb">,
286+
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
287+
[IntrNoMem]>;
288+
def int_ppc_altivec_vcmpnezb : GCCBuiltin<"__builtin_altivec_vcmpnezb">,
289+
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
290+
[IntrNoMem]>;
273291

274292
// Predicate Comparisons. The first operand specifies interpretation of CR6.
275293
def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">,
@@ -304,6 +322,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
304322
def int_ppc_altivec_vcmpgtuw_p : GCCBuiltin<"__builtin_altivec_vcmpgtuw_p">,
305323
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty],
306324
[IntrNoMem]>;
325+
def int_ppc_altivec_vcmpnew_p : GCCBuiltin<"__builtin_altivec_vcmpnew_p">,
326+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty],
327+
[IntrNoMem]>;
328+
def int_ppc_altivec_vcmpnezw_p : GCCBuiltin<"__builtin_altivec_vcmpnezw_p">,
329+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4i32_ty,llvm_v4i32_ty],
330+
[IntrNoMem]>;
307331

308332
def int_ppc_altivec_vcmpequh_p : GCCBuiltin<"__builtin_altivec_vcmpequh_p">,
309333
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty],
@@ -314,6 +338,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
314338
def int_ppc_altivec_vcmpgtuh_p : GCCBuiltin<"__builtin_altivec_vcmpgtuh_p">,
315339
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty],
316340
[IntrNoMem]>;
341+
def int_ppc_altivec_vcmpneh_p : GCCBuiltin<"__builtin_altivec_vcmpneh_p">,
342+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty],
343+
[IntrNoMem]>;
344+
def int_ppc_altivec_vcmpnezh_p : GCCBuiltin<"__builtin_altivec_vcmpnezh_p">,
345+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v8i16_ty,llvm_v8i16_ty],
346+
[IntrNoMem]>;
317347

318348
def int_ppc_altivec_vcmpequb_p : GCCBuiltin<"__builtin_altivec_vcmpequb_p">,
319349
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
@@ -324,6 +354,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
324354
def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">,
325355
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
326356
[IntrNoMem]>;
357+
def int_ppc_altivec_vcmpneb_p : GCCBuiltin<"__builtin_altivec_vcmpneb_p">,
358+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
359+
[IntrNoMem]>;
360+
def int_ppc_altivec_vcmpnezb_p : GCCBuiltin<"__builtin_altivec_vcmpnezb_p">,
361+
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
362+
[IntrNoMem]>;
327363
}
328364

329365
// Vector average.

‎lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 56 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -216,11 +216,17 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
216216
setOperationAction(ISD::FROUND, MVT::f32, Legal);
217217
}
218218

219-
// PowerPC does not have BSWAP, CTPOP or CTTZ
219+
// PowerPC does not have BSWAP
220+
// CTPOP or CTTZ were introduced in P8/P9 respectivelly
220221
setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
221-
setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
222222
setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
223-
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
223+
if (Subtarget.isISA3_0()) {
224+
setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
225+
setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
226+
} else {
227+
setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
228+
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
229+
}
224230

225231
if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
226232
setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
@@ -433,6 +439,12 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
433439
setOperationAction(ISD::CTLZ, VT, Expand);
434440
}
435441

442+
// Vector instructions introduced in P9
443+
if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
444+
setOperationAction(ISD::CTTZ, VT, Legal);
445+
else
446+
setOperationAction(ISD::CTTZ, VT, Expand);
447+
436448
// We promote all shuffles to v16i8.
437449
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
438450
AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
@@ -489,7 +501,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
489501
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
490502
setOperationAction(ISD::FPOW, VT, Expand);
491503
setOperationAction(ISD::BSWAP, VT, Expand);
492-
setOperationAction(ISD::CTTZ, VT, Expand);
493504
setOperationAction(ISD::VSELECT, VT, Expand);
494505
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
495506
setOperationAction(ISD::ROTL, VT, Expand);
@@ -7710,6 +7721,27 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
77107721
} else
77117722
return false;
77127723

7724+
break;
7725+
case Intrinsic::ppc_altivec_vcmpneb_p:
7726+
case Intrinsic::ppc_altivec_vcmpneh_p:
7727+
case Intrinsic::ppc_altivec_vcmpnew_p:
7728+
case Intrinsic::ppc_altivec_vcmpnezb_p:
7729+
case Intrinsic::ppc_altivec_vcmpnezh_p:
7730+
case Intrinsic::ppc_altivec_vcmpnezw_p:
7731+
if (Subtarget.hasP9Altivec()) {
7732+
switch(IntrinsicID) {
7733+
default: llvm_unreachable("Unknown comparison intrinsic.");
7734+
case Intrinsic::ppc_altivec_vcmpneb_p: CompareOpc = 7; break;
7735+
case Intrinsic::ppc_altivec_vcmpneh_p: CompareOpc = 71; break;
7736+
case Intrinsic::ppc_altivec_vcmpnew_p: CompareOpc = 135; break;
7737+
case Intrinsic::ppc_altivec_vcmpnezb_p: CompareOpc = 263; break;
7738+
case Intrinsic::ppc_altivec_vcmpnezh_p: CompareOpc = 327; break;
7739+
case Intrinsic::ppc_altivec_vcmpnezw_p: CompareOpc = 391; break;
7740+
}
7741+
isDot = 1;
7742+
} else
7743+
return false;
7744+
77137745
break;
77147746
case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
77157747
case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
@@ -7772,6 +7804,26 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
77727804
return false;
77737805

77747806
break;
7807+
case Intrinsic::ppc_altivec_vcmpneb:
7808+
case Intrinsic::ppc_altivec_vcmpneh:
7809+
case Intrinsic::ppc_altivec_vcmpnew:
7810+
case Intrinsic::ppc_altivec_vcmpnezb:
7811+
case Intrinsic::ppc_altivec_vcmpnezh:
7812+
case Intrinsic::ppc_altivec_vcmpnezw:
7813+
if (Subtarget.hasP9Altivec()) {
7814+
switch (IntrinsicID) {
7815+
default: llvm_unreachable("Unknown comparison intrinsic.");
7816+
case Intrinsic::ppc_altivec_vcmpneb: CompareOpc = 7; break;
7817+
case Intrinsic::ppc_altivec_vcmpneh: CompareOpc = 71; break;
7818+
case Intrinsic::ppc_altivec_vcmpnew: CompareOpc = 135; break;
7819+
case Intrinsic::ppc_altivec_vcmpnezb: CompareOpc = 263; break;
7820+
case Intrinsic::ppc_altivec_vcmpnezh: CompareOpc = 327; break;
7821+
case Intrinsic::ppc_altivec_vcmpnezw: CompareOpc = 391; break;
7822+
}
7823+
isDot = 0;
7824+
} else
7825+
return false;
7826+
break;
77757827
case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
77767828
case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
77777829
case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;

‎lib/Target/PowerPC/PPCInstrAltivec.td

Lines changed: 20 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1218,34 +1218,23 @@ def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
12181218
def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
12191219
let Predicates = [HasP9Altivec] in {
12201220

1221-
// Vector Compare Not Equal (Zero)
1222-
class P9VCMP<bits<10> xo, string asmstr, ValueType Ty>
1223-
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
1224-
IIC_VecFPCompare, []>;
1225-
class P9VCMPo<bits<10> xo, string asmstr, ValueType Ty>
1226-
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
1227-
IIC_VecFPCompare, []> {
1228-
let Defs = [CR6];
1229-
let RC = 1;
1230-
}
1231-
12321221
// i8 element comparisons.
1233-
def VCMPNEB : P9VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>;
1234-
def VCMPNEBo : P9VCMPo< 7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
1235-
def VCMPNEZB : P9VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
1236-
def VCMPNEZBo : P9VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
1222+
def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>;
1223+
def VCMPNEBo : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
1224+
def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
1225+
def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
12371226

12381227
// i16 element comparisons.
1239-
def VCMPNEH : P9VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>;
1240-
def VCMPNEHo : P9VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
1241-
def VCMPNEZH : P9VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
1242-
def VCMPNEZHo : P9VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
1228+
def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>;
1229+
def VCMPNEHo : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
1230+
def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
1231+
def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
12431232

12441233
// i32 element comparisons.
1245-
def VCMPNEW : P9VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>;
1246-
def VCMPNEWo : P9VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
1247-
def VCMPNEZW : P9VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
1248-
def VCMPNEZWo : P9VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
1234+
def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>;
1235+
def VCMPNEWo : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
1236+
def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
1237+
def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
12491238

12501239
// VX-Form: [PO VRT / UIM VRB XO].
12511240
// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
@@ -1288,10 +1277,14 @@ def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
12881277
def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
12891278
"vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
12901279
// Vector Count Trailing Zeros
1291-
def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", []>;
1292-
def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", []>;
1293-
def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", []>;
1294-
def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", []>;
1280+
def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
1281+
[(set v16i8:$vD, (cttz v16i8:$vB))]>;
1282+
def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
1283+
[(set v8i16:$vD, (cttz v8i16:$vB))]>;
1284+
def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
1285+
[(set v4i32:$vD, (cttz v4i32:$vB))]>;
1286+
def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
1287+
[(set v2i64:$vD, (cttz v2i64:$vB))]>;
12951288

12961289
// Vector Extend Sign
12971290
def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;

‎lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -852,6 +852,8 @@ def : InstAlias<"xxswapd $XT, $XB",
852852

853853
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
854854

855+
def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
856+
(v4i32 (XXLNOR $A, $A))>;
855857
let Predicates = [IsBigEndian] in {
856858
def : Pat<(v2f64 (scalar_to_vector f64:$A)),
857859
(v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;

‎test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll

Lines changed: 147 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,147 @@
1+
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
2+
; RUN: -verify-machineinstrs < %s | FileCheck %s
3+
4+
; Function Attrs: nounwind readnone
5+
define zeroext i32 @testCTZ32(i32 signext %a) {
6+
entry:
7+
%0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
8+
ret i32 %0
9+
; CHECK-LABEL: testCTZ32
10+
; CHECK: cnttzw 3, 3
11+
}
12+
13+
; Function Attrs: nounwind readnone
14+
declare i32 @llvm.cttz.i32(i32, i1)
15+
16+
; Function Attrs: nounwind readnone
17+
define zeroext i32 @testCTZ64(i64 %a) {
18+
entry:
19+
%0 = tail call i64 @llvm.cttz.i64(i64 %a, i1 false)
20+
%cast = trunc i64 %0 to i32
21+
ret i32 %cast
22+
; CHECK-LABEL: testCTZ64
23+
; CHECK: cnttzd 3, 3
24+
}
25+
26+
; Function Attrs: nounwind readnone
27+
declare i64 @llvm.cttz.i64(i64, i1)
28+
29+
; Function Attrs: nounwind readnone
30+
define <16 x i8> @testVCMPNEB(<16 x i8> %a, <16 x i8> %b) {
31+
entry:
32+
%0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8> %a, <16 x i8> %b)
33+
ret <16 x i8> %0
34+
; CHECK-LABEL: testVCMPNEB
35+
; CHECK: vcmpneb 2, 2
36+
}
37+
38+
; Function Attrs: nounwind readnone
39+
declare <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8>, <16 x i8>)
40+
41+
; Function Attrs: nounwind readnone
42+
define <16 x i8> @testVCMPNEZB(<16 x i8> %a, <16 x i8> %b) {
43+
entry:
44+
%0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8> %a, <16 x i8> %b)
45+
ret <16 x i8> %0
46+
; CHECK-LABEL: testVCMPNEZB
47+
; CHECK: vcmpnezb 2, 2
48+
}
49+
50+
; Function Attrs: nounwind readnone
51+
declare <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8>, <16 x i8>)
52+
53+
; Function Attrs: nounwind readnone
54+
define <8 x i16> @testVCMPNEH(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCMPNEH
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; CHECK: vcmpneh 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16>, <8 x i16>)
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; Function Attrs: nounwind readnone
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define <8 x i16> @testVCMPNEZH(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCMPNEZH
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; CHECK: vcmpnezh 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16>, <8 x i16>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCMPNEW(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCMPNEW
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; CHECK: vcmpnew 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32>, <4 x i32>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCMPNEZW(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCMPNEZW
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; CHECK: vcmpnezw 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32>, <4 x i32>)
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; Function Attrs: nounwind readnone
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define <16 x i8> @testVCNTTZB(<16 x i8> %a) {
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entry:
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%0 = tail call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)
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ret <16 x i8> %0
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; CHECK-LABEL: testVCNTTZB
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; CHECK: vctzb 2, 2
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}
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; Function Attrs: nounwind readnone
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define <8 x i16> @testVCNTTZH(<8 x i16> %a) {
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entry:
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%0 = tail call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCNTTZH
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; CHECK: vctzh 2, 2
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCNTTZW(<4 x i32> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCNTTZW
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; CHECK: vctzw 2, 2
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}
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; Function Attrs: nounwind readnone
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define <2 x i64> @testVCNTTZD(<2 x i64> %a) {
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entry:
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%0 = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
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ret <2 x i64> %0
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; CHECK-LABEL: testVCNTTZD
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; CHECK: vctzd 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)

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