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[AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.
Summary: This is patch [3/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: SjoerdMeijer Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45689 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330406 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -933,3 +933,24 @@ def ZZZZ_s : RegisterOperand<ZPR4, "printTypedVectorList<0,'s'>"> {
933933
def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
934934
let ParserMatchClass = ZPRVectorList<64, 4>;
935935
}
936+
937+
class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
938+
let Name = AsmOperandName # Scale;
939+
let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
940+
let DiagnosticType = "Invalid" # AsmOperandName # Scale;
941+
let RenderMethod = "addRegOperands";
942+
let ParserMethod = "tryParseGPROperand<true>";
943+
}
944+
945+
class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{
946+
let ParserMatchClass = !cast<AsmOperandClass>(Name);
947+
let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x'>";
948+
}
949+
950+
foreach Scale = [8, 16, 32, 64] in {
951+
def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">;
952+
def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>;
953+
954+
def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">;
955+
def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>;
956+
}

‎lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3823,6 +3823,22 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
38233823
ComputeAvailableFeatures(STI->getFeatureBits()));
38243824
return Error(Loc, "unrecognized instruction mnemonic" + Suggestion);
38253825
}
3826+
case Match_InvalidGPR64shifted8:
3827+
return Error(Loc, "register must be x0..x30 or xzr, without shift");
3828+
case Match_InvalidGPR64shifted16:
3829+
return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #1'");
3830+
case Match_InvalidGPR64shifted32:
3831+
return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #2'");
3832+
case Match_InvalidGPR64shifted64:
3833+
return Error(Loc, "register must be x0..x30 or xzr, with required shift 'lsl #3'");
3834+
case Match_InvalidGPR64NoXZRshifted8:
3835+
return Error(Loc, "register must be x0..x30 without shift");
3836+
case Match_InvalidGPR64NoXZRshifted16:
3837+
return Error(Loc, "register must be x0..x30 with required shift 'lsl #1'");
3838+
case Match_InvalidGPR64NoXZRshifted32:
3839+
return Error(Loc, "register must be x0..x30 with required shift 'lsl #2'");
3840+
case Match_InvalidGPR64NoXZRshifted64:
3841+
return Error(Loc, "register must be x0..x30 with required shift 'lsl #3'");
38263842
case Match_InvalidSVEPattern:
38273843
return Error(Loc, "invalid predicate pattern");
38283844
case Match_InvalidSVEPredicateAnyReg:
@@ -4268,6 +4284,14 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
42684284
case Match_InvalidLabel:
42694285
case Match_InvalidComplexRotationEven:
42704286
case Match_InvalidComplexRotationOdd:
4287+
case Match_InvalidGPR64shifted8:
4288+
case Match_InvalidGPR64shifted16:
4289+
case Match_InvalidGPR64shifted32:
4290+
case Match_InvalidGPR64shifted64:
4291+
case Match_InvalidGPR64NoXZRshifted8:
4292+
case Match_InvalidGPR64NoXZRshifted16:
4293+
case Match_InvalidGPR64NoXZRshifted32:
4294+
case Match_InvalidGPR64NoXZRshifted64:
42714295
case Match_InvalidSVEPredicateAnyReg:
42724296
case Match_InvalidSVEPattern:
42734297
case Match_InvalidSVEPredicateBReg:

‎lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,10 @@ static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
5555
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
5656
uint64_t Address,
5757
const void *Decoder);
58+
LLVM_ATTRIBUTE_UNUSED
59+
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60+
uint64_t Address,
61+
const void *Decoder);
5862
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
5963
uint64_t Address,
6064
const void *Decoder);
@@ -402,6 +406,17 @@ static const unsigned GPR64DecoderTable[] = {
402406
AArch64::LR, AArch64::XZR
403407
};
404408

409+
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
410+
uint64_t Addr,
411+
const void *Decoder) {
412+
if (RegNo > 30)
413+
return Fail;
414+
415+
unsigned Register = GPR64DecoderTable[RegNo];
416+
Inst.addOperand(MCOperand::createReg(Register));
417+
return Success;
418+
}
419+
405420
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
406421
uint64_t Addr,
407422
const void *Decoder) {

‎lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

Lines changed: 25 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -969,12 +969,9 @@ void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
969969
O << " #" << ShiftVal;
970970
}
971971

972-
void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
973-
raw_ostream &O, char SrcRegKind,
974-
unsigned Width) {
975-
unsigned SignExtend = MI->getOperand(OpNum).getImm();
976-
unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
977-
972+
static void printMemExtendImpl(bool SignExtend, bool DoShift,
973+
unsigned Width, char SrcRegKind,
974+
raw_ostream &O) {
978975
// sxtw, sxtx, uxtw or lsl (== uxtx)
979976
bool IsLSL = !SignExtend && SrcRegKind == 'x';
980977
if (IsLSL)
@@ -986,6 +983,28 @@ void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
986983
O << " #" << Log2_32(Width / 8);
987984
}
988985

986+
void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
987+
raw_ostream &O, char SrcRegKind,
988+
unsigned Width) {
989+
bool SignExtend = MI->getOperand(OpNum).getImm();
990+
bool DoShift = MI->getOperand(OpNum + 1).getImm();
991+
printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
992+
}
993+
994+
template <bool SignExtend, int ExtWidth, char SrcRegKind>
995+
void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
996+
unsigned OpNum,
997+
const MCSubtargetInfo &STI,
998+
raw_ostream &O) {
999+
printOperand(MI, OpNum, STI, O);
1000+
1001+
bool DoShift = ExtWidth != 8;
1002+
if (SignExtend || DoShift || SrcRegKind == 'w') {
1003+
O << ", ";
1004+
printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1005+
}
1006+
}
1007+
9891008
void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
9901009
const MCSubtargetInfo &STI,
9911010
raw_ostream &O) {

‎lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,9 @@ class AArch64InstPrinter : public MCInstPrinter {
9090
const MCSubtargetInfo &STI, raw_ostream &O) {
9191
printMemExtend(MI, OpNum, O, SrcRegKind, Width);
9292
}
93-
93+
template <bool SignedExtend, int ExtWidth, char SrcRegKind>
94+
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
95+
const MCSubtargetInfo &STI, raw_ostream &O);
9496
void printCondCode(const MCInst *MI, unsigned OpNum,
9597
const MCSubtargetInfo &STI, raw_ostream &O);
9698
void printInverseCondCode(const MCInst *MI, unsigned OpNum,

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