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[AMDGPU] Scalar Memory instructions TD refactoring
Differential revision: https://reviews.llvm.org/D23996 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280349 91177308-0d34-0410-b5e6-96231b3b80d8
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-398
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‎lib/Target/AMDGPU/CIInstructions.td

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Original file line numberDiff line numberDiff line change
@@ -71,14 +71,6 @@ defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
7171
>;
7272
} // End isCommutable = 1
7373

74-
75-
//===----------------------------------------------------------------------===//
76-
// SMRD Instructions
77-
//===----------------------------------------------------------------------===//
78-
79-
defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<0x1d, 0x22>,
80-
"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
81-
8274
//===----------------------------------------------------------------------===//
8375
// MUBUF Instructions
8476
//===----------------------------------------------------------------------===//

‎lib/Target/AMDGPU/SIInstrFormats.td

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@@ -199,60 +199,6 @@ class VOP3Common <dag outs, dag ins, string asm = "",
199199

200200
} // End Uses = [EXEC]
201201

202-
//===----------------------------------------------------------------------===//
203-
// Scalar operations
204-
//===----------------------------------------------------------------------===//
205-
206-
class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
207-
bits<7> sdst;
208-
bits<7> sbase;
209-
210-
let Inst{8} = imm;
211-
let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
213-
let Inst{26-22} = op;
214-
let Inst{31-27} = 0x18; //encoding
215-
}
216-
217-
class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
218-
bits<8> offset;
219-
let Inst{7-0} = offset;
220-
}
221-
222-
class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
223-
bits<8> soff;
224-
let Inst{7-0} = soff;
225-
}
226-
227-
228-
229-
class SMRD_IMMe_ci <bits<5> op> : Enc64 {
230-
bits<7> sdst;
231-
bits<7> sbase;
232-
bits<32> offset;
233-
234-
let Inst{7-0} = 0xff;
235-
let Inst{8} = 0;
236-
let Inst{14-9} = sbase{6-1};
237-
let Inst{21-15} = sdst;
238-
let Inst{26-22} = op;
239-
let Inst{31-27} = 0x18; //encoding
240-
let Inst{63-32} = offset;
241-
}
242-
243-
244-
class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
245-
InstSI<outs, ins, asm, pattern> {
246-
247-
let LGKM_CNT = 1;
248-
let SMRD = 1;
249-
let mayStore = 0;
250-
let mayLoad = 1;
251-
let hasSideEffects = 0;
252-
let UseNamedOperandTable = 1;
253-
let SchedRW = [WriteSMEM];
254-
}
255-
256202
//===----------------------------------------------------------------------===//
257203
// Vector ALU operations
258204
//===----------------------------------------------------------------------===//

‎lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 0 additions & 177 deletions
Original file line numberDiff line numberDiff line change
@@ -54,14 +54,6 @@ class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
5454
let VI3 = vi;
5555
}
5656

57-
// Specify an SMRD opcode for SI and SMEM opcode for VI
58-
59-
// FIXME: This should really be bits<5> si, Tablegen crashes if
60-
// parameter default value is other parameter with different bit size
61-
class smrd<bits<8> si, bits<8> vi = si> {
62-
field bits<5> SI = si{4-0};
63-
field bits<8> VI = vi;
64-
}
6557

6658
// Execpt for the NONE field, this must be kept in sync with the
6759
// SIEncodingFamily enum in AMDGPUInstrInfo.cpp
@@ -173,13 +165,6 @@ def mubuf_sextloadi16 : MubufLoad <sextloadi16>;
173165

174166
def mubuf_load_atomic : MubufLoad <atomic_load>;
175167

176-
def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
177-
auto Ld = cast<LoadSDNode>(N);
178-
return Ld->getAlignment() >= 4 &&
179-
Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
180-
static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
181-
}]>;
182-
183168
//===----------------------------------------------------------------------===//
184169
// PatFrags for global memory operations
185170
//===----------------------------------------------------------------------===//
@@ -477,8 +462,6 @@ def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
477462
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
478463
def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
479464

480-
def smrd_offset : NamedOperandU32<"SMRDOffset", NamedMatchClass<"SMRDOffset">>;
481-
def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", NamedMatchClass<"SMRDLiteralOffset">>;
482465

483466
def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
484467
def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
@@ -547,13 +530,6 @@ def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
547530
def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">;
548531
def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">;
549532

550-
def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
551-
def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
552-
def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
553-
def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
554-
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
555-
def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
556-
557533
def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
558534

559535
def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
@@ -640,159 +616,6 @@ multiclass EXP_m {
640616
}
641617
}
642618

643-
//===----------------------------------------------------------------------===//
644-
// Scalar classes
645-
//===----------------------------------------------------------------------===//
646-
647-
648-
//===----------------------------------------------------------------------===//
649-
// SMRD classes
650-
//===----------------------------------------------------------------------===//
651-
652-
class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
653-
SMRD <outs, ins, "", pattern>,
654-
SIMCInstr<opName, SIEncodingFamily.NONE> {
655-
let isPseudo = 1;
656-
let isCodeGenOnly = 1;
657-
}
658-
659-
class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
660-
string asm> :
661-
SMRD <outs, ins, asm, []>,
662-
SMRD_IMMe <op>,
663-
SIMCInstr<opName, SIEncodingFamily.SI> {
664-
let AssemblerPredicates = [isSICI];
665-
let DecoderNamespace = "SICI";
666-
let DisableDecoder = DisableSIDecoder;
667-
}
668-
669-
class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
670-
string asm> :
671-
SMRD <outs, ins, asm, []>,
672-
SMRD_SOFFe <op>,
673-
SIMCInstr<opName, SIEncodingFamily.SI> {
674-
let AssemblerPredicates = [isSICI];
675-
let DecoderNamespace = "SICI";
676-
let DisableDecoder = DisableSIDecoder;
677-
}
678-
679-
680-
class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
681-
string asm, list<dag> pattern = []> :
682-
SMRD <outs, ins, asm, pattern>,
683-
SMEM_IMMe_vi <op>,
684-
SIMCInstr<opName, SIEncodingFamily.VI> {
685-
let AssemblerPredicates = [isVI];
686-
let DecoderNamespace = "VI";
687-
let DisableDecoder = DisableVIDecoder;
688-
}
689-
690-
class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
691-
string asm, list<dag> pattern = []> :
692-
SMRD <outs, ins, asm, pattern>,
693-
SMEM_SOFFe_vi <op>,
694-
SIMCInstr<opName, SIEncodingFamily.VI> {
695-
let AssemblerPredicates = [isVI];
696-
let DecoderNamespace = "VI";
697-
let DisableDecoder = DisableVIDecoder;
698-
}
699-
700-
701-
multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
702-
string asm, list<dag> pattern> {
703-
704-
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
705-
706-
def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>;
707-
708-
// glc is only applicable to scalar stores, which are not yet
709-
// implemented.
710-
let glc = 0 in {
711-
def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>;
712-
}
713-
}
714-
715-
multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins,
716-
string asm, list<dag> pattern> {
717-
718-
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
719-
720-
def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>;
721-
722-
// glc is only applicable to scalar stores, which are not yet
723-
// implemented.
724-
let glc = 0 in {
725-
def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>;
726-
}
727-
}
728-
729-
multiclass SMRD_Special <smrd op, string opName, dag outs,
730-
int sdst_ = ?,
731-
string opStr = "",
732-
list<dag> pattern = []> {
733-
let hasSideEffects = 1 in {
734-
def "" : SMRD_Pseudo <opName, outs, (ins), pattern>;
735-
736-
let sbase = 0, soff = 0, sdst = sdst_ in {
737-
def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>;
738-
739-
let glc = 0 in {
740-
def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>;
741-
}
742-
}
743-
}
744-
}
745-
746-
multiclass SMRD_Inval <smrd op, string opName,
747-
SDPatternOperator node> {
748-
let mayStore = 1 in {
749-
defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>;
750-
}
751-
}
752-
753-
class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
754-
SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> {
755-
let hasSideEffects = 1;
756-
let mayStore = 1;
757-
let sbase = 0;
758-
let sdst = 0;
759-
let glc = 0;
760-
let soff = 0;
761-
}
762-
763-
class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> :
764-
SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
765-
opName#" $sdst", [(set i64:$sdst, (node))]> {
766-
let hasSideEffects = 1;
767-
let mayStore = ?;
768-
let mayLoad = ?;
769-
let sbase = 0;
770-
let glc = 0;
771-
let soff = 0;
772-
}
773-
774-
multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
775-
RegisterClass dstClass> {
776-
defm _IMM : SMRD_IMM_m <
777-
op, opName#"_IMM", (outs dstClass:$sdst),
778-
(ins baseClass:$sbase, smrd_offset:$offset),
779-
opName#" $sdst, $sbase, $offset", []
780-
>;
781-
782-
def _IMM_ci : SMRD <
783-
(outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
784-
opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
785-
let AssemblerPredicates = [isCIOnly];
786-
let DecoderNamespace = "CI";
787-
}
788-
789-
defm _SGPR : SMRD_SOFF_m <
790-
op, opName#"_SGPR", (outs dstClass:$sdst),
791-
(ins baseClass:$sbase, SReg_32:$soff),
792-
opName#" $sdst, $sbase, $soff", []
793-
>;
794-
}
795-
796619
//===----------------------------------------------------------------------===//
797620
// Vector ALU classes
798621
//===----------------------------------------------------------------------===//

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