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Zlatko BuljanZlatko Buljan
Zlatko Buljan
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Zlatko Buljan
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[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions
Differential Revision: http://reviews.llvm.org/D16676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267694 91177308-0d34-0410-b5e6-96231b3b80d8
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9 files changed

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-57
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9 files changed

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‎lib/Target/Mips/MicroMips32r6InstrInfo.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -990,7 +990,9 @@ class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
990990
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
991991
MicroMipsR6Inst16;
992992
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
993-
MMR6Arch<"subu16">, MicroMipsR6Inst16;
993+
MMR6Arch<"subu16">, MicroMipsR6Inst16 {
994+
int AddedComplexity = 1;
995+
}
994996
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
995997
MMR6Arch<"xor16">;
996998

@@ -1478,3 +1480,5 @@ def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
14781480

14791481
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
14801482
(SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1483+
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1484+
(SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;

‎lib/Target/Mips/MicroMips64r6InstrInfo.td

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,8 @@ class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
4141
class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
4242
class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
4343
class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
44+
class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
45+
class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
4446

4547
//===----------------------------------------------------------------------===//
4648
//
@@ -124,6 +126,24 @@ class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
124126
IsAsCheapAsAMove;
125127
class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
126128

129+
class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
130+
InstrItinClass Itin = NoItinerary,
131+
SDPatternOperator OpNode = null_frag>
132+
: MipsR6Inst {
133+
dag OutOperandList = (outs RO:$rd);
134+
dag InOperandList = (ins RO:$rs, RO:$rt);
135+
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
136+
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
137+
InstrItinClass Itinerary = Itin;
138+
Format Form = FrmR;
139+
string BaseOpcode = instr_asm;
140+
let isCommutable = 0;
141+
let isReMaterializable = 1;
142+
let TwoOperandAliasConstraint = "$rd = $rs";
143+
}
144+
class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
145+
class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
146+
127147
class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
128148

129149
//===----------------------------------------------------------------------===//
@@ -178,6 +198,10 @@ let DecoderNamespace = "MicroMipsR6" in {
178198
ISA_MICROMIPS64R6;
179199
def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
180200
ISA_MICROMIPS64R6;
201+
def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
202+
ISA_MICROMIPS64R6;
203+
def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
204+
ISA_MICROMIPS64R6;
181205
}
182206

183207
//===----------------------------------------------------------------------===//
@@ -222,6 +246,10 @@ def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
222246
def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
223247
def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
224248

249+
// Carry pattern
250+
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
251+
(DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
252+
225253
//===----------------------------------------------------------------------===//
226254
//
227255
// Instruction aliases
@@ -253,3 +281,15 @@ def : MipsInstAlias<"dsubu $rs, $imm",
253281
GPR64Opnd:$rs,
254282
InvertedImOperand64:$imm),
255283
0>, ISA_MICROMIPS64R6;
284+
def : MipsInstAlias<"dneg $rt, $rs",
285+
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
286+
ISA_MICROMIPS64R6;
287+
def : MipsInstAlias<"dneg $rt",
288+
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
289+
ISA_MICROMIPS64R6;
290+
def : MipsInstAlias<"dnegu $rt, $rs",
291+
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
292+
ISA_MICROMIPS64R6;
293+
def : MipsInstAlias<"dnegu $rt",
294+
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
295+
ISA_MICROMIPS64R6;

‎lib/Target/Mips/MicroMipsInstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -996,6 +996,8 @@ def : MipsPat<(load addrimm4lsl2:$addr),
996996
(LW16_MM addrimm4lsl2:$addr)>;
997997
def : MipsPat<(load addr:$addr),
998998
(LW_MM addr:$addr)>;
999+
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1000+
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
9991001

10001002
//===----------------------------------------------------------------------===//
10011003
// MicroMips instruction aliases

‎lib/Target/Mips/Mips64InstrInfo.td

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -120,11 +120,11 @@ let AdditionalPredicates = [NotInMicroMips] in {
120120
ADD_FM<0, 0x2c>, ISA_MIPS3;
121121
def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
122122
ADD_FM<0, 0x2d>, ISA_MIPS3;
123+
def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
124+
ISA_MIPS3;
125+
def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
126+
ISA_MIPS3;
123127
}
124-
def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
125-
ISA_MIPS3;
126-
def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
127-
ISA_MIPS3;
128128

129129
let isCodeGenOnly = 1 in {
130130
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
@@ -554,9 +554,9 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
554554
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
555555

556556
// Carry pattern
557-
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
558-
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
559557
let AdditionalPredicates = [NotInMicroMips] in {
558+
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
559+
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
560560
def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
561561
(DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;
562562
def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
@@ -611,15 +611,17 @@ let AdditionalPredicates = [NotInMicroMips] in {
611611
def : MipsInstAlias<"dsll $rd, $rt, $rs",
612612
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
613613
ISA_MIPS3;
614-
def : MipsInstAlias<"dneg $rt, $rs",
615-
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
616-
ISA_MIPS3;
617-
def : MipsInstAlias<"dneg $rt",
618-
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
619-
ISA_MIPS3;
620-
def : MipsInstAlias<"dnegu $rt, $rs",
621-
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
622-
ISA_MIPS3;
614+
let AdditionalPredicates = [NotInMicroMips] in {
615+
def : MipsInstAlias<"dneg $rt, $rs",
616+
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
617+
ISA_MIPS3;
618+
def : MipsInstAlias<"dneg $rt",
619+
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
620+
ISA_MIPS3;
621+
def : MipsInstAlias<"dnegu $rt, $rs",
622+
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
623+
ISA_MIPS3;
624+
}
623625
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
624626
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
625627
InvertedImOperand64:$imm),

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1668,14 +1668,14 @@ let AdditionalPredicates = [NotInMicroMips] in {
16681668
/// Arithmetic Instructions (3-Operand, R-Type)
16691669
def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
16701670
ADD_FM<0, 0x21>;
1671-
def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1671+
def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
16721672
ADD_FM<0, 0x23>;
16731673
}
16741674
let Defs = [HI0, LO0] in
16751675
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
16761676
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
16771677
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1678-
def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1678+
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
16791679
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
16801680
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
16811681
let AdditionalPredicates = [NotInMicroMips] in {
@@ -2404,8 +2404,10 @@ def : MipsPat<(i32 imm:$imm),
24042404
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
24052405

24062406
// Carry MipsPatterns
2407-
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
2408-
(SUBu GPR32:$lhs, GPR32:$rhs)>;
2407+
let AdditionalPredicates = [NotInMicroMips] in {
2408+
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
2409+
(SUBu GPR32:$lhs, GPR32:$rhs)>;
2410+
}
24092411
def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
24102412
(ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP;
24112413
def : MipsPat<(addc GPR32:$src, immSExt16:$imm),

‎test/CodeGen/Mips/llvm-ir/sub.ll

Lines changed: 77 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,53 @@
11
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2-
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
2+
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
3+
; RUN: -check-prefix=NOT-MM
34
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4-
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
5+
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
6+
; RUN: -check-prefix=NOT-MM
57
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
8+
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
9+
; RUN: -check-prefix=NOT-MM
710
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
8-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
11+
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
12+
; RUN: -check-prefix=NOT-MM
913
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
10-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
14+
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
15+
; RUN: -check-prefix=NOT-MM
1116
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
12-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
17+
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
18+
; RUN: -check-prefix=NOT-MM
19+
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
20+
; RUN: -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
21+
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
22+
; RUN: -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
1323
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
14-
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
24+
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
1525
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
16-
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
26+
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
1727
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
18-
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
28+
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
1929
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
20-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
30+
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
2131
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
22-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
32+
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
2333
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
24-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
34+
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
2535
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
26-
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
36+
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
37+
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
38+
; RUN: -check-prefix=GP64 -check-prefix=MM
2739

2840
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
2941
entry:
3042
; ALL-LABEL: sub_i1:
3143

32-
; ALL: subu $[[T0:[0-9]+]], $4, $5
33-
; ALL: sll $[[T0]], $[[T0]], 31
34-
; ALL: sra $2, $[[T0]], 31
44+
; NOT-MM: subu $[[T0:[0-9]+]], $4, $5
45+
; NOT-MM: sll $[[T0]], $[[T0]], 31
46+
; NOT-MM: sra $2, $[[T0]], 31
47+
48+
; MM: subu16 $[[T0:[0-9]+]], $4, $5
49+
; MM: sll $[[T1:[0-9]+]], $[[T0]], 31
50+
; MM: sra $[[T0]], $[[T1]], 31
3551

3652
%r = sub i1 %a, %b
3753
ret i1 %r
@@ -48,6 +64,9 @@ entry:
4864
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
4965
; R2-R6: seb $2, $[[T0:[0-9]+]]
5066

67+
; MM: subu16 $[[T0:[0-9]+]], $4, $5
68+
; MM: seb $[[T0]], $[[T0]]
69+
5170
%r = sub i8 %a, %b
5271
ret i8 %r
5372
}
@@ -63,6 +82,9 @@ entry:
6382
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
6483
; R2-R6: seh $2, $[[T0:[0-9]+]]
6584

85+
; MM: subu16 $[[T0:[0-9]+]], $4, $5
86+
; MM: seh $[[T0]], $[[T0]]
87+
6688
%r = sub i16 %a, %b
6789
ret i16 %r
6890
}
@@ -71,7 +93,9 @@ define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
7193
entry:
7294
; ALL-LABEL: sub_i32:
7395

74-
; ALL: subu $2, $4, $5
96+
; NOT-MM: subu $2, $4, $5
97+
98+
; MM: subu16 $2, $4, $5
7599

76100
%r = sub i32 %a, %b
77101
ret i32 %r
@@ -96,26 +120,42 @@ define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
96120
entry:
97121
; ALL-LABEL: sub_i128:
98122

99-
; GP32: lw $[[T0:[0-9]+]], 20($sp)
100-
; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]]
101-
; GP32: lw $[[T2:[0-9]+]], 16($sp)
102-
; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
103-
; GP32: lw $[[T4:[0-9]+]], 24($sp)
104-
; GP32: lw $[[T5:[0-9]+]], 28($sp)
105-
; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]]
106-
; GP32: subu $2, $4, $[[T3]]
107-
; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]]
108-
; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
109-
; GP32: subu $3, $5, $[[T9]]
110-
; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]]
111-
; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
112-
; GP32: subu $4, $6, $[[T11]]
113-
; GP32: move $5, $[[T6]]
114-
115-
; GP64: dsubu $3, $5, $7
116-
; GP64: sltu $[[T0:[0-9]+]], $5, $7
117-
; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
118-
; GP64: dsubu $2, $4, $[[T1]]
123+
; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp)
124+
; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
125+
; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp)
126+
; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
127+
; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp)
128+
; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp)
129+
; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]]
130+
; GP32-NOT-MM: subu $2, $4, $[[T3]]
131+
; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
132+
; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
133+
; GP32-NOT-MM: subu $3, $5, $[[T9]]
134+
; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
135+
; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
136+
; GP32-NOT-MM: subu $4, $6, $[[T11]]
137+
; GP32-NOT-MM: move $5, $[[T6]]
138+
139+
; GP32-MM: lw $[[T0:[0-9]+]], 20($sp)
140+
; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
141+
; GP32-MM: lw $[[T3:[0-9]+]], 16($sp)
142+
; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]]
143+
; GP32-MM: lw $[[T4:[0-9]+]], 28($sp)
144+
; GP32-MM: subu $[[T1]], $7, $[[T4]]
145+
; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]]
146+
; GP32-MM: lw $[[T5]], 24($sp)
147+
; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
148+
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
149+
; GP32-MM: subu $[[T0]], $5, $[[T0]]
150+
; GP32-MM: sltu $[[T2]], $7, $[[T4]]
151+
; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]]
152+
; GP32-MM: subu $[[T5]], $6, $[[T5]]
153+
; GP32-MM: move $[[T2]], $[[T1]]
154+
155+
; GP64: dsubu $3, $5, $7
156+
; GP64: sltu $[[T0:[0-9]+]], $5, $7
157+
; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
158+
; GP64: dsubu $2, $4, $[[T1]]
119159

120160
%r = sub i128 %a, %b
121161
ret i128 %r

‎test/MC/Disassembler/Mips/micromips64r6/valid.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -232,3 +232,9 @@
232232
0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
233233
0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
234234
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
235+
0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
236+
0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
237+
0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
238+
0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
239+
0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
240+
0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5

‎test/MC/Mips/micromips64r6/invalid.s

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,3 +176,7 @@
176176
sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
177177
srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
178178
srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
179+
dneg $7, 5 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
180+
dneg 4 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
181+
dnegu $1, 3 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
182+
dnegu 7 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

‎test/MC/Mips/micromips64r6/valid.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,5 +223,11 @@ a:
223223
sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
224224
sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
225225
srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
226+
dsub $1, $2, $3 # CHECK: dsub $1, $2, $3 # encoding: [0x58,0x62,0x09,0x90]
227+
dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0]
228+
dneg $7, $15 # CHECK: dneg $7, $15 # encoding: [0x59,0xe0,0x39,0x90]
229+
dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90]
230+
dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0]
231+
dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0]
226232

227233
1:

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