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[SystemZ] Use LLGT(R) instructions
This adds support for the 31-to-64-bit zero extension instructions LLGT and LLGTR and uses them for code generation where appropriate. Since this operation can also be performed via RISBG, we have to update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT over RISBG in case both are possible. The patch includes some simplification to the tryRISBGZero code; this is not intended to cause any (further) functional change in codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286585 91177308-0d34-0410-b5e6-96231b3b80d8
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9 files changed

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9 files changed

+260
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lines changed

‎lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Lines changed: 36 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -935,49 +935,45 @@ bool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
935935
Count += 1;
936936
if (Count == 0)
937937
return false;
938-
if (Count == 1) {
939-
// Prefer to use normal shift instructions over RISBG, since they can handle
940-
// all cases and are sometimes shorter.
941-
if (N->getOpcode() != ISD::AND)
942-
return false;
943938

944-
// Prefer register extensions like LLC over RISBG. Also prefer to start
945-
// out with normal ANDs if one instruction would be enough. We can convert
946-
// these ANDs into an RISBG later if a three-address instruction is useful.
947-
if (VT == MVT::i32 ||
948-
RISBG.Mask == 0xff ||
949-
RISBG.Mask == 0xffff ||
950-
SystemZ::isImmLF(~RISBG.Mask) ||
951-
SystemZ::isImmHF(~RISBG.Mask)) {
952-
// Force the new mask into the DAG, since it may include known-one bits.
953-
auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
954-
if (MaskN->getZExtValue() != RISBG.Mask) {
955-
SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);
956-
N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
957-
SelectCode(N);
958-
return true;
959-
}
960-
return false;
961-
}
962-
}
939+
// Prefer to use normal shift instructions over RISBG, since they can handle
940+
// all cases and are sometimes shorter.
941+
if (Count == 1 && N->getOpcode() != ISD::AND)
942+
return false;
963943

964-
// If the RISBG operands require no rotation and just masks the bottom
965-
// 8/16 bits, attempt to convert this to a LLC zero extension.
966-
if (RISBG.Rotate == 0 && (RISBG.Mask == 0xff || RISBG.Mask == 0xffff)) {
967-
unsigned OpCode = (RISBG.Mask == 0xff ? SystemZ::LLGCR : SystemZ::LLGHR);
968-
if (VT == MVT::i32) {
969-
if (Subtarget->hasHighWord())
970-
OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCRMux : SystemZ::LLHRMux);
971-
else
972-
OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCR : SystemZ::LLHR);
944+
// Prefer register extensions like LLC over RISBG. Also prefer to start
945+
// out with normal ANDs if one instruction would be enough. We can convert
946+
// these ANDs into an RISBG later if a three-address instruction is useful.
947+
if (RISBG.Rotate == 0) {
948+
bool PreferAnd = false;
949+
// Prefer AND for any 32-bit and-immediate operation.
950+
if (VT == MVT::i32)
951+
PreferAnd = true;
952+
// As well as for any 64-bit operation that can be implemented via LLC(R),
953+
// LLH(R), LLGT(R), or one of the and-immediate instructions.
954+
else if (RISBG.Mask == 0xff ||
955+
RISBG.Mask == 0xffff ||
956+
RISBG.Mask == 0x7fffffff ||
957+
SystemZ::isImmLF(~RISBG.Mask) ||
958+
SystemZ::isImmHF(~RISBG.Mask))
959+
PreferAnd = true;
960+
if (PreferAnd) {
961+
// Replace the current node with an AND. Note that the current node
962+
// might already be that same AND, in which case it is already CSE'd
963+
// with it, and we must not call ReplaceNode.
964+
SDValue In = convertTo(DL, VT, RISBG.Input);
965+
SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT);
966+
SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask);
967+
if (N != New.getNode()) {
968+
insertDAGNode(CurDAG, N, Mask);
969+
insertDAGNode(CurDAG, N, New);
970+
ReplaceNode(N, New.getNode());
971+
N = New.getNode();
972+
}
973+
// Now, select the machine opcode to implement this operation.
974+
SelectCode(N);
975+
return true;
973976
}
974-
975-
SDValue In = convertTo(DL, VT, RISBG.Input);
976-
SDValue New = convertTo(
977-
DL, VT, SDValue(CurDAG->getMachineNode(OpCode, DL, VT, In), 0));
978-
ReplaceUses(N, New.getNode());
979-
CurDAG->RemoveDeadNode(N);
980-
return true;
981977
}
982978

983979
unsigned Opcode = SystemZ::RISBG;

‎lib/Target/SystemZ/SystemZInstrInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -575,6 +575,14 @@ def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
575575
def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
576576
def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
577577

578+
// 31-to-64-bit zero extensions.
579+
def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>;
580+
def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>;
581+
def : Pat<(and GR64:$src, 0x7fffffff),
582+
(LLGTR GR64:$src)>;
583+
def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff),
584+
(LLGT bdxaddr20only:$src)>;
585+
578586
//===----------------------------------------------------------------------===//
579587
// Truncations
580588
//===----------------------------------------------------------------------===//

‎lib/Target/SystemZ/SystemZScheduleZ13.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -237,12 +237,12 @@ def : InstRW<[FXa, LSU, Lat5], (instregex "LG(H|F)RL$")>;
237237

238238
def : InstRW<[FXa], (instregex "LLCR(Mux)?$")>;
239239
def : InstRW<[FXa], (instregex "LLHR(Mux)?$")>;
240-
def : InstRW<[FXa], (instregex "LLG(C|H|F)R$")>;
240+
def : InstRW<[FXa], (instregex "LLG(C|H|F|T)R$")>;
241241
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
242242
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
243243
def : InstRW<[FXa, LSU, Lat5], (instregex "LL(C|H)H$")>;
244244
def : InstRW<[LSU], (instregex "LLHRL$")>;
245-
def : InstRW<[LSU], (instregex "LLG(C|H|F|HRL|FRL)$")>;
245+
def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
246246

247247
//===----------------------------------------------------------------------===//
248248
// Truncations

‎lib/Target/SystemZ/SystemZScheduleZ196.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -212,12 +212,12 @@ def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
212212

213213
def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
214214
def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
215-
def : InstRW<[FXU], (instregex "LLG(C|F|H)R$")>;
215+
def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
216216
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
217217
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
218218
def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
219219
def : InstRW<[LSU], (instregex "LLHRL$")>;
220-
def : InstRW<[LSU], (instregex "LLG(C|F|H|FRL|HRL)$")>;
220+
def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
221221

222222
//===----------------------------------------------------------------------===//
223223
// Truncations

‎lib/Target/SystemZ/SystemZScheduleZEC12.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -214,12 +214,12 @@ def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
214214

215215
def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
216216
def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
217-
def : InstRW<[FXU], (instregex "LLG(C|H|F)R$")>;
217+
def : InstRW<[FXU], (instregex "LLG(C|H|F|T)R$")>;
218218
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
219219
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
220220
def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
221221
def : InstRW<[LSU], (instregex "LLHRL$")>;
222-
def : InstRW<[LSU], (instregex "LLG(C|H|F|HRL|FRL)$")>;
222+
def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
223223

224224
//===----------------------------------------------------------------------===//
225225
// Truncations

‎test/CodeGen/SystemZ/int-conv-12.ll

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,133 @@
1+
; Test 31-to-64 bit zero extensions.
2+
;
3+
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4+
5+
; Test register extension, starting with an i64.
6+
define i64 @f1(i64 %a) {
7+
; CHECK-LABEL: f1:
8+
; CHECK: llgtr %r2, %r2
9+
; CHECK: br %r14
10+
%ext = and i64 %a, 2147483647
11+
ret i64 %ext
12+
}
13+
14+
; Test register extension, starting with an i32.
15+
define i64 @f2(i32 %a) {
16+
; CHECK-LABEL: f2:
17+
; CHECK: llgtr %r2, %r2
18+
; CHECK: br %r14
19+
%and = and i32 %a, 2147483647
20+
%ext = zext i32 %and to i64
21+
ret i64 %ext
22+
}
23+
24+
; ... and the other way around.
25+
define i64 @f3(i32 %a) {
26+
; CHECK-LABEL: f3:
27+
; CHECK: llgtr %r2, %r2
28+
; CHECK: br %r14
29+
%ext = zext i32 %a to i64
30+
%and = and i64 %ext, 2147483647
31+
ret i64 %and
32+
}
33+
34+
; Check LLGT with no displacement.
35+
define i64 @f4(i32 *%src) {
36+
; CHECK-LABEL: f4:
37+
; CHECK: llgt %r2, 0(%r2)
38+
; CHECK: br %r14
39+
%word = load i32, i32 *%src
40+
%ext = zext i32 %word to i64
41+
%and = and i64 %ext, 2147483647
42+
ret i64 %and
43+
}
44+
45+
; ... and the other way around.
46+
define i64 @f5(i32 *%src) {
47+
; CHECK-LABEL: f5:
48+
; CHECK: llgt %r2, 0(%r2)
49+
; CHECK: br %r14
50+
%word = load i32, i32 *%src
51+
%and = and i32 %word, 2147483647
52+
%ext = zext i32 %and to i64
53+
ret i64 %ext
54+
}
55+
56+
; Check the high end of the LLGT range.
57+
define i64 @f6(i32 *%src) {
58+
; CHECK-LABEL: f6:
59+
; CHECK: llgt %r2, 524284(%r2)
60+
; CHECK: br %r14
61+
%ptr = getelementptr i32, i32 *%src, i64 131071
62+
%word = load i32 , i32 *%ptr
63+
%ext = zext i32 %word to i64
64+
%and = and i64 %ext, 2147483647
65+
ret i64 %and
66+
}
67+
68+
; Check the next word up, which needs separate address logic.
69+
; Other sequences besides this one would be OK.
70+
define i64 @f7(i32 *%src) {
71+
; CHECK-LABEL: f7:
72+
; CHECK: agfi %r2, 524288
73+
; CHECK: llgt %r2, 0(%r2)
74+
; CHECK: br %r14
75+
%ptr = getelementptr i32, i32 *%src, i64 131072
76+
%word = load i32 , i32 *%ptr
77+
%ext = zext i32 %word to i64
78+
%and = and i64 %ext, 2147483647
79+
ret i64 %and
80+
}
81+
82+
; Check the high end of the negative LLGT range.
83+
define i64 @f8(i32 *%src) {
84+
; CHECK-LABEL: f8:
85+
; CHECK: llgt %r2, -4(%r2)
86+
; CHECK: br %r14
87+
%ptr = getelementptr i32, i32 *%src, i64 -1
88+
%word = load i32 , i32 *%ptr
89+
%ext = zext i32 %word to i64
90+
%and = and i64 %ext, 2147483647
91+
ret i64 %and
92+
}
93+
94+
; Check the low end of the LLGT range.
95+
define i64 @f9(i32 *%src) {
96+
; CHECK-LABEL: f9:
97+
; CHECK: llgt %r2, -524288(%r2)
98+
; CHECK: br %r14
99+
%ptr = getelementptr i32, i32 *%src, i64 -131072
100+
%word = load i32 , i32 *%ptr
101+
%ext = zext i32 %word to i64
102+
%and = and i64 %ext, 2147483647
103+
ret i64 %and
104+
}
105+
106+
; Check the next word down, which needs separate address logic.
107+
; Other sequences besides this one would be OK.
108+
define i64 @f10(i32 *%src) {
109+
; CHECK-LABEL: f10:
110+
; CHECK: agfi %r2, -524292
111+
; CHECK: llgt %r2, 0(%r2)
112+
; CHECK: br %r14
113+
%ptr = getelementptr i32, i32 *%src, i64 -131073
114+
%word = load i32 , i32 *%ptr
115+
%ext = zext i32 %word to i64
116+
%and = and i64 %ext, 2147483647
117+
ret i64 %and
118+
}
119+
120+
; Check that LLGT allows an index.
121+
define i64 @f11(i64 %src, i64 %index) {
122+
; CHECK-LABEL: f11:
123+
; CHECK: llgt %r2, 524287(%r3,%r2)
124+
; CHECK: br %r14
125+
%add1 = add i64 %src, %index
126+
%add2 = add i64 %add1, 524287
127+
%ptr = inttoptr i64 %add2 to i32 *
128+
%word = load i32 , i32 *%ptr
129+
%ext = zext i32 %word to i64
130+
%and = and i64 %ext, 2147483647
131+
ret i64 %and
132+
}
133+

‎test/MC/Disassembler/SystemZ/insns.txt

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5356,6 +5356,45 @@
53565356
# CHECK: llgf %r15, 0
53575357
0xe3 0xf0 0x00 0x00 0x00 0x16
53585358

5359+
# CHECK: llgtr %r0, %r15
5360+
0xb9 0x17 0x00 0x0f
5361+
5362+
# CHECK: llgtr %r7, %r8
5363+
0xb9 0x17 0x00 0x78
5364+
5365+
# CHECK: llgtr %r15, %r0
5366+
0xb9 0x17 0x00 0xf0
5367+
5368+
# CHECK: llgt %r0, -524288
5369+
0xe3 0x00 0x00 0x00 0x80 0x17
5370+
5371+
# CHECK: llgt %r0, -1
5372+
0xe3 0x00 0x0f 0xff 0xff 0x17
5373+
5374+
# CHECK: llgt %r0, 0
5375+
0xe3 0x00 0x00 0x00 0x00 0x17
5376+
5377+
# CHECK: llgt %r0, 1
5378+
0xe3 0x00 0x00 0x01 0x00 0x17
5379+
5380+
# CHECK: llgt %r0, 524287
5381+
0xe3 0x00 0x0f 0xff 0x7f 0x17
5382+
5383+
# CHECK: llgt %r0, 0(%r1)
5384+
0xe3 0x00 0x10 0x00 0x00 0x17
5385+
5386+
# CHECK: llgt %r0, 0(%r15)
5387+
0xe3 0x00 0xf0 0x00 0x00 0x17
5388+
5389+
# CHECK: llgt %r0, 524287(%r1,%r15)
5390+
0xe3 0x01 0xff 0xff 0x7f 0x17
5391+
5392+
# CHECK: llgt %r0, 524287(%r15,%r1)
5393+
0xe3 0x0f 0x1f 0xff 0x7f 0x17
5394+
5395+
# CHECK: llgt %r15, 0
5396+
0xe3 0xf0 0x00 0x00 0x00 0x17
5397+
53595398
# CHECK: llghr %r0, %r15
53605399
0xb9 0x85 0x00 0x0f
53615400

‎test/MC/SystemZ/insn-bad.s

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2080,6 +2080,14 @@
20802080
llgc %r0, -524289
20812081
llgc %r0, 524288
20822082

2083+
#CHECK: error: invalid operand
2084+
#CHECK: llgt %r0, -524289
2085+
#CHECK: error: invalid operand
2086+
#CHECK: llgt %r0, 524288
2087+
2088+
llgt %r0, -524289
2089+
llgt %r0, 524288
2090+
20832091
#CHECK: error: invalid operand
20842092
#CHECK: llgf %r0, -524289
20852093
#CHECK: error: invalid operand

‎test/MC/SystemZ/insn-good.s

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6741,6 +6741,36 @@
67416741
llgcr %r7, %r8
67426742
llgcr %r15, %r0
67436743

6744+
#CHECK: llgt %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x17]
6745+
#CHECK: llgt %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x17]
6746+
#CHECK: llgt %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x17]
6747+
#CHECK: llgt %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x17]
6748+
#CHECK: llgt %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x17]
6749+
#CHECK: llgt %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x17]
6750+
#CHECK: llgt %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x17]
6751+
#CHECK: llgt %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x17]
6752+
#CHECK: llgt %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x17]
6753+
#CHECK: llgt %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x17]
6754+
6755+
llgt %r0, -524288
6756+
llgt %r0, -1
6757+
llgt %r0, 0
6758+
llgt %r0, 1
6759+
llgt %r0, 524287
6760+
llgt %r0, 0(%r1)
6761+
llgt %r0, 0(%r15)
6762+
llgt %r0, 524287(%r1,%r15)
6763+
llgt %r0, 524287(%r15,%r1)
6764+
llgt %r15, 0
6765+
6766+
#CHECK: llgtr %r0, %r15 # encoding: [0xb9,0x17,0x00,0x0f]
6767+
#CHECK: llgtr %r7, %r8 # encoding: [0xb9,0x17,0x00,0x78]
6768+
#CHECK: llgtr %r15, %r0 # encoding: [0xb9,0x17,0x00,0xf0]
6769+
6770+
llgtr %r0, %r15
6771+
llgtr %r7, %r8
6772+
llgtr %r15, %r0
6773+
67446774
#CHECK: llgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x16]
67456775
#CHECK: llgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x16]
67466776
#CHECK: llgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x16]

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