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Commit 9209299

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author
Zvi Rackover
committed
[X86] Optimization for replacing LEA with MOV at frame index elimination time
Summary: Replace a LEA instruction of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx' MOV is preferable over LEA because usually there are more issue-slots available to execute MOVs than LEAs. Latest processors also support zero-latency MOVs. Fixes pr29022. Reviewers: hfinkel, delena, igorb, myatsina, mkuper Differential Revision: https://reviews.llvm.org/D24705 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282385 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 56b0418 commit 9209299

18 files changed

+83
-38
lines changed

‎lib/Target/X86/X86RegisterInfo.cpp

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -595,6 +595,35 @@ bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
595595
llvm_unreachable("Unused function on X86. Otherwise need a test case.");
596596
}
597597

598+
// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
599+
// of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
600+
// TODO: In this case we should be really trying first to entirely eliminate
601+
// this instruction which is a plain copy.
602+
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
603+
MachineInstr &MI = *II;
604+
unsigned Opc = II->getOpcode();
605+
// Check if this is a LEA of the form 'lea (%esp), %ebx'
606+
if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
607+
MI.getOperand(2).getImm() != 1 ||
608+
MI.getOperand(3).getReg() != X86::NoRegister ||
609+
MI.getOperand(4).getImm() != 0 ||
610+
MI.getOperand(5).getReg() != X86::NoRegister)
611+
return false;
612+
unsigned BasePtr = MI.getOperand(1).getReg();
613+
// In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
614+
// be replaced with a 32-bit operand MOV which will zero extend the upper
615+
// 32-bits of the super register.
616+
if (Opc == X86::LEA64_32r)
617+
BasePtr = getX86SubSuperRegister(BasePtr, 32);
618+
unsigned NewDestReg = MI.getOperand(0).getReg();
619+
const X86InstrInfo *TII =
620+
MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
621+
TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
622+
MI.getOperand(1).isKill());
623+
MI.eraseFromParent();
624+
return true;
625+
}
626+
598627
void
599628
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
600629
int SPAdj, unsigned FIOperandNum,
@@ -669,7 +698,8 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
669698
int Offset = FIOffset + Imm;
670699
assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
671700
"Requesting 64-bit offset in 32-bit immediate!");
672-
MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
701+
if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
702+
MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
673703
} else {
674704
// Offset is symbolic. This is extremely rare.
675705
uint64_t Offset = FIOffset +

‎test/CodeGen/X86/avx-intel-ocl.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ declare i32 @func_int(i32, i32)
2525
; X64-LABEL: testf16_inp
2626
; X64: vaddps {{.*}}, {{%ymm[0-1]}}
2727
; X64: vaddps {{.*}}, {{%ymm[0-1]}}
28-
; X64: leaq {{.*}}(%rsp), %rdi
28+
; X64: movq %rsp, %rdi
2929
; X64: call
3030
; X64: ret
3131

‎test/CodeGen/X86/avx512-intel-ocl.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ declare i32 @func_int(i32, i32)
2222

2323
; X64-LABEL: testf16_inp
2424
; X64: vaddps {{.*}}, {{%zmm[0-1]}}
25-
; X64: leaq {{.*}}(%rsp), %rdi
25+
; X64: movq %rsp, %rdi
2626
; X64: call
2727
; X64: ret
2828

‎test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
;
77
; CHECK: callq _Z3fooPcjPKc
88
; CHECK: callq _Z3fooPcjPKc
9-
; CHECK: leaq (%rsp), %rdi
9+
; CHECK: movq %rsp, %rdi
1010
; CHECK: movl $4, %esi
1111
; CHECK: testl {{%[a-z]+}}, {{%[a-z]+}}
1212
; CHECK: je .LBB0_4

‎test/CodeGen/X86/dynamic-allocas-VLAs.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ entry:
3838
; CHECK: subq ${{[0-9]+}}, %rsp
3939
;
4040
; CHECK: leaq {{[0-9]*}}(%rsp), %rdi
41-
; CHECK: leaq {{[0-9]*}}(%rsp), %rsi
41+
; CHECK: movq %rsp, %rsi
4242
; CHECK: callq _t2_helper
4343
;
4444
; CHECK: movq %rbp, %rsp
@@ -89,7 +89,7 @@ entry:
8989
; CHECK: movq %rsp, %rbx
9090
;
9191
; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
92-
; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
92+
; CHECK: movq %rbx, %rdx
9393
; CHECK: callq _t4_helper
9494
;
9595
; CHECK: leaq -{{[0-9]+}}(%rbp), %rsp

‎test/CodeGen/X86/extractelement-index.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -414,7 +414,7 @@ define i8 @extractelement_v32i8_var(<32 x i8> %a, i256 %i) nounwind {
414414
; SSE-NEXT: subq $64, %rsp
415415
; SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
416416
; SSE-NEXT: movaps %xmm0, (%rsp)
417-
; SSE-NEXT: leaq (%rsp), %rax
417+
; SSE-NEXT: movq %rsp, %rax
418418
; SSE-NEXT: movb (%rdi,%rax), %al
419419
; SSE-NEXT: movq %rbp, %rsp
420420
; SSE-NEXT: popq %rbp
@@ -427,7 +427,7 @@ define i8 @extractelement_v32i8_var(<32 x i8> %a, i256 %i) nounwind {
427427
; AVX-NEXT: andq $-32, %rsp
428428
; AVX-NEXT: subq $64, %rsp
429429
; AVX-NEXT: vmovaps %ymm0, (%rsp)
430-
; AVX-NEXT: leaq (%rsp), %rax
430+
; AVX-NEXT: movq %rsp, %rax
431431
; AVX-NEXT: movb (%rdi,%rax), %al
432432
; AVX-NEXT: movq %rbp, %rsp
433433
; AVX-NEXT: popq %rbp

‎test/CodeGen/X86/fast-isel-x86-64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@ entry:
254254
call void @test20sret(%struct.a* sret %tmp)
255255
ret void
256256
; CHECK-LABEL: test20:
257-
; CHECK: leaq (%rsp), %rdi
257+
; CHECK: movq %rsp, %rdi
258258
; CHECK: callq _test20sret
259259
}
260260
declare void @test20sret(%struct.a* sret)

‎test/CodeGen/X86/fast-isel-x86.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ entry:
8383
ret void
8484
; CHECK-LABEL: test4:
8585
; CHECK: subl $28
86-
; CHECK: leal (%esp), %ecx
86+
; CHECK: movl %esp, %ecx
8787
; CHECK: calll _test4fastccsret
8888
; CHECK: addl $28
8989
}

‎test/CodeGen/X86/frameaddr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ entry:
1919
; CHECK-W64-LABEL: test1
2020
; CHECK-W64: push
2121
; CHECK-W64-NEXT: movq %rsp, %rbp
22-
; CHECK-W64-NEXT: leaq (%rbp), %rax
22+
; CHECK-W64-NEXT: movq %rbp, %rax
2323
; CHECK-W64-NEXT: pop
2424
; CHECK-W64-NEXT: ret
2525
; CHECK-64-LABEL: test1
@@ -54,7 +54,7 @@ entry:
5454
; CHECK-W64-LABEL: test2
5555
; CHECK-W64: push
5656
; CHECK-W64-NEXT: movq %rsp, %rbp
57-
; CHECK-W64-NEXT: leaq (%rbp), %rax
57+
; CHECK-W64-NEXT: movq %rbp, %rax
5858
; CHECK-W64-NEXT: pop
5959
; CHECK-W64-NEXT: ret
6060
; CHECK-64-LABEL: test2

‎test/CodeGen/X86/lea-opt-memop-check-1.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define void @test1(i8* nocapture readonly %src, i32 %len) #0 {
2121
%call1 = tail call <4 x float> @_mm_castsi128_ps(<2 x i64> %tmp0)
2222
ret void
2323
; CHECK-LABEL: test1:
24-
; CHECK: leal{{.*}}
24+
; CHECK: movl %esp,
2525
; CHECK: calll _memcpy
2626
; CHECK: movaps __xmm@{{[0-9a-f]+}}, %xmm1
2727
; CHECK: calll __mm_xor_si128

‎test/CodeGen/X86/local_stack_symbol_ordering.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@
6767
; X64: callq check_a
6868
; X64: callq bar1
6969
; X64: callq bar1
70-
; X64: leaq (%rsp), %rdi
70+
; X64: movq %rsp, %rdi
7171
; X64: callq check_f
7272
; X64: callq bar1
7373
; X64: callq bar3

‎test/CodeGen/X86/pr29022.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
; RUN: llc < %s -mcpu=skx -mtriple x86_64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
2+
; RUN: llc < %s -mcpu=skx -mtriple=x86_64-linux-gnux32 -verify-machineinstrs | FileCheck %s --check-prefix=X32
3+
4+
define i32 @A() {
5+
; CHECK: movq %rsp, %rdi
6+
; CHECK-NEXT: call
7+
8+
; X32: movl %esp, %edi
9+
; X32-NEXT: call
10+
%alloc = alloca i32, align 8
11+
%call = call i32 @foo(i32* %alloc)
12+
ret i32 %call
13+
}
14+
15+
declare i32 @foo(i32*)

‎test/CodeGen/X86/sse-intel-ocl.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ declare <16 x float> @func_float16(<16 x float>, <16 x float>)
2727
; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
2828
; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
2929
; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
30-
; NOT_WIN: leaq {{.*}}(%rsp), %rdi
30+
; NOT_WIN: movq %rsp, %rdi
3131
; NOT_WIN: call
3232
; NOT_WIN: ret
3333

‎test/CodeGen/X86/sse-intrinsics-fast-isel.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -813,7 +813,7 @@ define i32 @test_MM_GET_EXCEPTION_MASK() nounwind {
813813
; X32-LABEL: test_MM_GET_EXCEPTION_MASK:
814814
; X32: # BB#0:
815815
; X32-NEXT: pushl %eax
816-
; X32-NEXT: leal (%esp), %eax
816+
; X32-NEXT: movl %esp, %eax
817817
; X32-NEXT: stmxcsr (%eax)
818818
; X32-NEXT: movl (%esp), %eax
819819
; X32-NEXT: andl $8064, %eax # imm = 0x1F80
@@ -840,7 +840,7 @@ define i32 @test_MM_GET_EXCEPTION_STATE() nounwind {
840840
; X32-LABEL: test_MM_GET_EXCEPTION_STATE:
841841
; X32: # BB#0:
842842
; X32-NEXT: pushl %eax
843-
; X32-NEXT: leal (%esp), %eax
843+
; X32-NEXT: movl %esp, %eax
844844
; X32-NEXT: stmxcsr (%eax)
845845
; X32-NEXT: movl (%esp), %eax
846846
; X32-NEXT: andl $63, %eax
@@ -866,7 +866,7 @@ define i32 @test_MM_GET_FLUSH_ZERO_MODE() nounwind {
866866
; X32-LABEL: test_MM_GET_FLUSH_ZERO_MODE:
867867
; X32: # BB#0:
868868
; X32-NEXT: pushl %eax
869-
; X32-NEXT: leal (%esp), %eax
869+
; X32-NEXT: movl %esp, %eax
870870
; X32-NEXT: stmxcsr (%eax)
871871
; X32-NEXT: movl (%esp), %eax
872872
; X32-NEXT: andl $32768, %eax # imm = 0x8000
@@ -892,7 +892,7 @@ define i32 @test_MM_GET_ROUNDING_MODE() nounwind {
892892
; X32-LABEL: test_MM_GET_ROUNDING_MODE:
893893
; X32: # BB#0:
894894
; X32-NEXT: pushl %eax
895-
; X32-NEXT: leal (%esp), %eax
895+
; X32-NEXT: movl %esp, %eax
896896
; X32-NEXT: stmxcsr (%eax)
897897
; X32-NEXT: movl (%esp), %eax
898898
; X32-NEXT: andl $24576, %eax # imm = 0x6000
@@ -918,7 +918,7 @@ define i32 @test_mm_getcsr() nounwind {
918918
; X32-LABEL: test_mm_getcsr:
919919
; X32: # BB#0:
920920
; X32-NEXT: pushl %eax
921-
; X32-NEXT: leal (%esp), %eax
921+
; X32-NEXT: movl %esp, %eax
922922
; X32-NEXT: stmxcsr (%eax)
923923
; X32-NEXT: movl (%esp), %eax
924924
; X32-NEXT: popl %ecx
@@ -1427,7 +1427,7 @@ define void @test_MM_SET_EXCEPTION_MASK(i32 %a0) nounwind {
14271427
; X32: # BB#0:
14281428
; X32-NEXT: pushl %eax
14291429
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1430-
; X32-NEXT: leal (%esp), %ecx
1430+
; X32-NEXT: movl %esp, %ecx
14311431
; X32-NEXT: stmxcsr (%ecx)
14321432
; X32-NEXT: movl (%esp), %edx
14331433
; X32-NEXT: andl $-8065, %edx # imm = 0xE07F
@@ -1464,7 +1464,7 @@ define void @test_MM_SET_EXCEPTION_STATE(i32 %a0) nounwind {
14641464
; X32: # BB#0:
14651465
; X32-NEXT: pushl %eax
14661466
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1467-
; X32-NEXT: leal (%esp), %ecx
1467+
; X32-NEXT: movl %esp, %ecx
14681468
; X32-NEXT: stmxcsr (%ecx)
14691469
; X32-NEXT: movl (%esp), %edx
14701470
; X32-NEXT: andl $-64, %edx
@@ -1500,7 +1500,7 @@ define void @test_MM_SET_FLUSH_ZERO_MODE(i32 %a0) nounwind {
15001500
; X32: # BB#0:
15011501
; X32-NEXT: pushl %eax
15021502
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1503-
; X32-NEXT: leal (%esp), %ecx
1503+
; X32-NEXT: movl %esp, %ecx
15041504
; X32-NEXT: stmxcsr (%ecx)
15051505
; X32-NEXT: movl (%esp), %edx
15061506
; X32-NEXT: andl $-32769, %edx # imm = 0xFFFF7FFF
@@ -1580,7 +1580,7 @@ define void @test_MM_SET_ROUNDING_MODE(i32 %a0) nounwind {
15801580
; X32: # BB#0:
15811581
; X32-NEXT: pushl %eax
15821582
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1583-
; X32-NEXT: leal (%esp), %ecx
1583+
; X32-NEXT: movl %esp, %ecx
15841584
; X32-NEXT: stmxcsr (%ecx)
15851585
; X32-NEXT: movl (%esp), %edx
15861586
; X32-NEXT: andl $-24577, %edx # imm = 0x9FFF
@@ -1655,7 +1655,7 @@ define void @test_mm_setcsr(i32 %a0) nounwind {
16551655
; X32: # BB#0:
16561656
; X32-NEXT: pushl %eax
16571657
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1658-
; X32-NEXT: leal (%esp), %ecx
1658+
; X32-NEXT: movl %esp, %ecx
16591659
; X32-NEXT: movl %eax, (%esp)
16601660
; X32-NEXT: ldmxcsr (%ecx)
16611661
; X32-NEXT: popl %eax

‎test/CodeGen/X86/swift-return.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,15 +38,15 @@ declare swiftcc { i16, i8 } @gen(i32)
3838
; in memroy. The caller provides space for the return value and passes
3939
; the address in %rax. The first input argument will be in %rdi.
4040
; CHECK-LABEL: test2:
41-
; CHECK: leaq (%rsp), %rax
41+
; CHECK: movq %rsp, %rax
4242
; CHECK: callq gen2
4343
; CHECK: movl (%rsp)
4444
; CHECK-DAG: addl 4(%rsp)
4545
; CHECK-DAG: addl 8(%rsp)
4646
; CHECK-DAG: addl 12(%rsp)
4747
; CHECK-DAG: addl 16(%rsp)
4848
; CHECK-O0-LABEL: test2:
49-
; CHECK-O0-DAG: leaq (%rsp), %rax
49+
; CHECK-O0-DAG: movq %rsp, %rax
5050
; CHECK-O0: callq gen2
5151
; CHECK-O0-DAG: movl (%rsp)
5252
; CHECK-O0-DAG: movl 4(%rsp)

‎test/CodeGen/X86/win32_sret.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ entry:
138138
; The this pointer goes to ECX.
139139
; (through %ecx in the -O0 build).
140140
; WIN32: leal {{[0-9]*}}(%esp), %e{{[a-d]}}x
141-
; WIN32: leal {{[0-9]*}}(%esp), %ecx
141+
; WIN32: {{leal [1-9]+\(%esp\)|movl %esp}}, %ecx
142142
; WIN32: {{pushl %e[a-d]x|movl %e[a-d]x, \(%esp\)}}
143143
; WIN32-NEXT: calll "?foo@C5@@QAE?AUS5@@XZ"
144144
; WIN32: retl
@@ -158,16 +158,16 @@ define void @test6_f(%struct.test6* %x) nounwind {
158158

159159

160160
; The sret pointer is (%esp)
161-
; WIN32: leal {{4?}}(%esp), %eax
161+
; WIN32: {{leal 4\(%esp\)|movl %esp}}, %eax
162162
; WIN32-NEXT: {{pushl %eax|movl %eax, \(%esp\)}}
163163

164164
; The sret pointer is %ecx
165165
; The %x argument is moved to (%esp). It will be the this pointer.
166-
; MINGW_X86: leal {{4?}}(%esp), %ecx
166+
; MINGW_X86: {{leal 4\(%esp\)|movl %esp}}, %ecx
167167
; MINGW_X86-NEXT: {{pushl 16\(%esp\)|movl %eax, \(%esp\)}}
168168
; MINGW_X86-NEXT: calll _test6_g
169169

170-
; CYGWIN: leal {{4?}}(%esp), %ecx
170+
; CYGWIN: {{leal 4\(%esp\)|movl %esp}}, %ecx
171171
; CYGWIN-NEXT: {{pushl 16\(%esp\)|movl %eax, \(%esp\)}}
172172
; CYGWIN-NEXT: calll _test6_g
173173

@@ -191,11 +191,11 @@ define void @test7_f(%struct.test7* %x) nounwind {
191191
; CYGWIN: movl {{16|20}}(%esp), %ecx
192192

193193
; The sret pointer is (%esp)
194-
; WIN32: leal {{4?}}(%esp), %eax
194+
; WIN32: {{leal 4\(%esp\)|movl %esp}}, %eax
195195
; WIN32-NEXT: {{pushl %eax|movl %eax, \(%esp\)}}
196-
; MINGW_X86: leal {{4?}}(%esp), %eax
196+
; MINGW_X86: {{leal 4\(%esp\)|movl %esp}}, %eax
197197
; MINGW_X86-NEXT: {{pushl %eax|movl %eax, \(%esp\)}}
198-
; CYGWIN: leal {{4?}}(%esp), %eax
198+
; CYGWIN: {{leal 4\(%esp\)|movl %esp}}, %eax
199199
; CYGWIN-NEXT: {{pushl %eax|movl %eax, \(%esp\)}}
200200

201201
%tmp = alloca %struct.test7, align 4

‎test/CodeGen/X86/win64_frame.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ define i32 @f8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "no-frame-pointer-elim"="
110110
%gep = getelementptr [300 x i8], [300 x i8]* %alloca, i32 0, i32 0
111111
call void @external(i8* %gep)
112112
; CHECK: subq $32, %rsp
113-
; CHECK: leaq (%rbx), %rcx
113+
; CHECK: movq %rbx, %rcx
114114
; CHECK: callq external
115115
; CHECK: addq $32, %rsp
116116

‎test/DebugInfo/COFF/inlining.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@
170170
; OBJ: PtrParent: 0x0
171171
; OBJ: PtrEnd: 0x0
172172
; OBJ: PtrNext: 0x0
173-
; OBJ: CodeSize: 0x3D
173+
; OBJ: CodeSize: 0x3C
174174
; OBJ: DbgStart: 0x0
175175
; OBJ: DbgEnd: 0x0
176176
; OBJ: FunctionType: baz (0x1004)
@@ -189,7 +189,7 @@
189189
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x8, LineOffset: 1}
190190
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x7, LineOffset: 1}
191191
; OBJ-NEXT: ChangeLineOffset: 1
192-
; OBJ-NEXT: ChangeCodeOffset: 0x1E
192+
; OBJ-NEXT: ChangeCodeOffset: 0x1D
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; OBJ-NEXT: ChangeCodeLength: 0x7
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; OBJ: ]
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; OBJ: }
@@ -199,7 +199,7 @@
199199
; OBJ: Inlinee: foo (0x1003)
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; OBJ: BinaryAnnotations [
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; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xF, LineOffset: 1}
202-
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xA, LineOffset: 1}
202+
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x9, LineOffset: 1}
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; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x6, LineOffset: 1}
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; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x7, LineOffset: 1}
205205
; OBJ-NEXT: ChangeCodeLength: 0x7

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