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[globalisel][aarch64] Prefix PartialMappingIdx enumerators with 'PMI_' to fit coding standards.
This also stops things like 'None' polluting the llvm::AArch64 namespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288799 91177308-0d34-0410-b5e6-96231b3b80d8
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+70
-66
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2 files changed

+70
-66
lines changed

‎lib/Target/AArch64/AArch64GenRegisterBankInfo.def

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -26,18 +26,18 @@ RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
2626

2727
// PartialMappings.
2828
enum PartialMappingIdx {
29-
None = -1,
30-
GPR32 = 0,
31-
GPR64,
32-
FPR32,
33-
FPR64,
34-
FPR128,
35-
FPR256,
36-
FPR512,
37-
FirstGPR = GPR32,
38-
LastGPR = GPR64,
39-
FirstFPR = FPR32,
40-
LastFPR = FPR512
29+
PMI_None = -1,
30+
PMI_GPR32 = 0,
31+
PMI_GPR64,
32+
PMI_FPR32,
33+
PMI_FPR64,
34+
PMI_FPR128,
35+
PMI_FPR256,
36+
PMI_FPR512,
37+
PMI_FirstGPR = PMI_GPR32,
38+
PMI_LastGPR = PMI_GPR64,
39+
PMI_FirstFPR = PMI_FPR32,
40+
PMI_LastFPR = PMI_FPR512
4141
};
4242

4343
static unsigned getRegBankBaseIdxOffset(unsigned Size) {
@@ -115,7 +115,7 @@ RegisterBankInfo::ValueMapping ValMappings[] {
115115
/// \pre \p RBIdx != PartialMappingIdx::None
116116
const RegisterBankInfo::ValueMapping *
117117
getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
118-
assert(RBIdx != PartialMappingIdx::None && "No mapping needed for that");
118+
assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
119119
unsigned ValMappingIdx = First3OpsIdx +
120120
(RBIdx + getRegBankBaseIdxOffset(Size)) *
121121
ValueMappingIdx::DistanceBetweenRegBanks;
@@ -133,14 +133,14 @@ getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
133133
/// otherwise it is on FPR. Same thing for \p SrcIsGPR.
134134
const RegisterBankInfo::ValueMapping *
135135
getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) {
136-
PartialMappingIdx DstRBIdx = DstIsGPR ? FirstGPR : FirstFPR;
137-
PartialMappingIdx SrcRBIdx = SrcIsGPR ? FirstGPR : FirstFPR;
136+
PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
137+
PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
138138
if (DstRBIdx == SrcRBIdx)
139139
return getValueMapping(DstRBIdx, Size);
140140
assert(Size <= 64 && "GPR cannot handle that size");
141141
unsigned ValMappingIdx =
142142
FirstCrossRegCpyIdx +
143-
(DstRBIdx - FirstGPR + getRegBankBaseIdxOffset(Size)) *
143+
(DstRBIdx - PMI_FirstGPR + getRegBankBaseIdxOffset(Size)) *
144144
ValueMappingIdx::DistanceBetweenCrossRegCpy;
145145
assert(ValMappingIdx >= AArch64::FirstCrossRegCpyIdx &&
146146
ValMappingIdx <= AArch64::LastCrossRegCpyIdx &&

‎lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Lines changed: 54 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -83,32 +83,32 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
8383

8484
// Check that the TableGen'ed like file is in sync we our expectations.
8585
// First, the Idx.
86-
assert(AArch64::PartialMappingIdx::GPR32 ==
87-
AArch64::PartialMappingIdx::FirstGPR &&
86+
assert(AArch64::PartialMappingIdx::PMI_GPR32 ==
87+
AArch64::PartialMappingIdx::PMI_FirstGPR &&
8888
"GPR32 index not first in the GPR list");
89-
assert(AArch64::PartialMappingIdx::GPR64 ==
90-
AArch64::PartialMappingIdx::LastGPR &&
89+
assert(AArch64::PartialMappingIdx::PMI_GPR64 ==
90+
AArch64::PartialMappingIdx::PMI_LastGPR &&
9191
"GPR64 index not last in the GPR list");
92-
assert(AArch64::PartialMappingIdx::FirstGPR <=
93-
AArch64::PartialMappingIdx::LastGPR &&
92+
assert(AArch64::PartialMappingIdx::PMI_FirstGPR <=
93+
AArch64::PartialMappingIdx::PMI_LastGPR &&
9494
"GPR list is backward");
95-
assert(AArch64::PartialMappingIdx::FPR32 ==
96-
AArch64::PartialMappingIdx::FirstFPR &&
95+
assert(AArch64::PartialMappingIdx::PMI_FPR32 ==
96+
AArch64::PartialMappingIdx::PMI_FirstFPR &&
9797
"FPR32 index not first in the FPR list");
98-
assert(AArch64::PartialMappingIdx::FPR512 ==
99-
AArch64::PartialMappingIdx::LastFPR &&
98+
assert(AArch64::PartialMappingIdx::PMI_FPR512 ==
99+
AArch64::PartialMappingIdx::PMI_LastFPR &&
100100
"FPR512 index not last in the FPR list");
101-
assert(AArch64::PartialMappingIdx::FirstFPR <=
102-
AArch64::PartialMappingIdx::LastFPR &&
101+
assert(AArch64::PartialMappingIdx::PMI_FirstFPR <=
102+
AArch64::PartialMappingIdx::PMI_LastFPR &&
103103
"FPR list is backward");
104-
assert(AArch64::PartialMappingIdx::FPR32 + 1 ==
105-
AArch64::PartialMappingIdx::FPR64 &&
106-
AArch64::PartialMappingIdx::FPR64 + 1 ==
107-
AArch64::PartialMappingIdx::FPR128 &&
108-
AArch64::PartialMappingIdx::FPR128 + 1 ==
109-
AArch64::PartialMappingIdx::FPR256 &&
110-
AArch64::PartialMappingIdx::FPR256 + 1 ==
111-
AArch64::PartialMappingIdx::FPR512 &&
104+
assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 ==
105+
AArch64::PartialMappingIdx::PMI_FPR64 &&
106+
AArch64::PartialMappingIdx::PMI_FPR64 + 1 ==
107+
AArch64::PartialMappingIdx::PMI_FPR128 &&
108+
AArch64::PartialMappingIdx::PMI_FPR128 + 1 ==
109+
AArch64::PartialMappingIdx::PMI_FPR256 &&
110+
AArch64::PartialMappingIdx::PMI_FPR256 + 1 ==
111+
AArch64::PartialMappingIdx::PMI_FPR512 &&
112112
"FPR indices not properly ordered");
113113
// Now, the content.
114114
// Check partial mapping.
@@ -121,22 +121,22 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
121121
Map.RegBank == &RB && #Idx " is incorrectly initialized"); \
122122
} while (0)
123123

124-
CHECK_PARTIALMAP(GPR32, 0, 32, RBGPR);
125-
CHECK_PARTIALMAP(GPR64, 0, 64, RBGPR);
126-
CHECK_PARTIALMAP(FPR32, 0, 32, RBFPR);
127-
CHECK_PARTIALMAP(FPR64, 0, 64, RBFPR);
128-
CHECK_PARTIALMAP(FPR128, 0, 128, RBFPR);
129-
CHECK_PARTIALMAP(FPR256, 0, 256, RBFPR);
130-
CHECK_PARTIALMAP(FPR512, 0, 512, RBFPR);
124+
CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
125+
CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
126+
CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
127+
CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
128+
CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
129+
CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
130+
CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
131131

132132
// Check value mapping.
133133
#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
134134
do { \
135135
AArch64::PartialMappingIdx PartialMapBaseIdx = \
136-
AArch64::PartialMappingIdx::RBName##Size; \
136+
AArch64::PartialMappingIdx::PMI_##RBName##Size; \
137137
(void) PartialMapBaseIdx; \
138138
const ValueMapping &Map = \
139-
AArch64::getValueMapping(AArch64::First##RBName, Size)[Offset]; \
139+
AArch64::getValueMapping(AArch64::PMI_First##RBName, Size)[Offset]; \
140140
(void) Map; \
141141
assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \
142142
Map.NumBreakDowns == 1 && #RBName #Size \
@@ -173,14 +173,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
173173
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
174174
do { \
175175
AArch64::PartialMappingIdx PartialMapDstIdx = \
176-
AArch64::PartialMappingIdx::RBNameDst##Size; \
176+
AArch64::PartialMappingIdx::PMI_##RBNameDst##Size; \
177177
AArch64::PartialMappingIdx PartialMapSrcIdx = \
178-
AArch64::PartialMappingIdx::RBNameSrc##Size; \
178+
AArch64::PartialMappingIdx::PMI_##RBNameSrc##Size; \
179179
(void) PartialMapDstIdx; \
180180
(void) PartialMapSrcIdx; \
181181
const ValueMapping *Map = AArch64::getCopyMapping( \
182-
AArch64::First##RBNameDst == AArch64::FirstGPR, \
183-
AArch64::First##RBNameSrc == AArch64::FirstGPR, Size); \
182+
AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR, \
183+
AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size); \
184184
(void) Map; \
185185
assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] && \
186186
Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
@@ -283,10 +283,12 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
283283
break;
284284
InstructionMappings AltMappings;
285285
InstructionMapping GPRMapping(
286-
/*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstGPR, Size),
286+
/*ID*/ 1, /*Cost*/ 1,
287+
AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
287288
/*NumOperands*/ 3);
288289
InstructionMapping FPRMapping(
289-
/*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstFPR, Size),
290+
/*ID*/ 2, /*Cost*/ 1,
291+
AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
290292
/*NumOperands*/ 3);
291293

292294
AltMappings.emplace_back(std::move(GPRMapping));
@@ -342,15 +344,17 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
342344
InstructionMappings AltMappings;
343345
InstructionMapping GPRMapping(
344346
/*ID*/ 1, /*Cost*/ 1,
345-
getOperandsMapping({AArch64::getValueMapping(AArch64::FirstGPR, Size),
346-
// Addresses are GPR 64-bit.
347-
AArch64::getValueMapping(AArch64::FirstGPR, 64)}),
347+
getOperandsMapping(
348+
{AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
349+
// Addresses are GPR 64-bit.
350+
AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
348351
/*NumOperands*/ 2);
349352
InstructionMapping FPRMapping(
350353
/*ID*/ 2, /*Cost*/ 1,
351-
getOperandsMapping({AArch64::getValueMapping(AArch64::FirstFPR, Size),
352-
// Addresses are GPR 64-bit.
353-
AArch64::getValueMapping(AArch64::FirstGPR, 64)}),
354+
getOperandsMapping(
355+
{AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
356+
// Addresses are GPR 64-bit.
357+
AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
354358
/*NumOperands*/ 2);
355359

356360
AltMappings.emplace_back(std::move(GPRMapping));
@@ -431,7 +435,7 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(const MachineInstr &MI) {
431435
#endif // End NDEBUG.
432436

433437
AArch64::PartialMappingIdx RBIdx =
434-
IsFPR ? AArch64::FirstFPR : AArch64::FirstGPR;
438+
IsFPR ? AArch64::PMI_FirstFPR : AArch64::PMI_FirstGPR;
435439

436440
return InstructionMapping{DefaultMappingID, 1,
437441
AArch64::getValueMapping(RBIdx, Size), NumOperands};
@@ -508,9 +512,9 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
508512
// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
509513
// For floating-point instructions, scalars go in FPRs.
510514
if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
511-
OpRegBankIdx[Idx] = AArch64::FirstFPR;
515+
OpRegBankIdx[Idx] = AArch64::PMI_FirstFPR;
512516
else
513-
OpRegBankIdx[Idx] = AArch64::FirstGPR;
517+
OpRegBankIdx[Idx] = AArch64::PMI_FirstGPR;
514518
}
515519

516520
unsigned Cost = 1;
@@ -519,18 +523,18 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
519523
switch (Opc) {
520524
case TargetOpcode::G_SITOFP:
521525
case TargetOpcode::G_UITOFP: {
522-
OpRegBankIdx = {AArch64::FirstFPR, AArch64::FirstGPR};
526+
OpRegBankIdx = {AArch64::PMI_FirstFPR, AArch64::PMI_FirstGPR};
523527
break;
524528
}
525529
case TargetOpcode::G_FPTOSI:
526530
case TargetOpcode::G_FPTOUI: {
527-
OpRegBankIdx = {AArch64::FirstGPR, AArch64::FirstFPR};
531+
OpRegBankIdx = {AArch64::PMI_FirstGPR, AArch64::PMI_FirstFPR};
528532
break;
529533
}
530534
case TargetOpcode::G_FCMP: {
531-
OpRegBankIdx = {AArch64::FirstGPR,
532-
/* Predicate */ AArch64::PartialMappingIdx::None,
533-
AArch64::FirstFPR, AArch64::FirstFPR};
535+
OpRegBankIdx = {AArch64::PMI_FirstGPR,
536+
/* Predicate */ AArch64::PMI_None, AArch64::PMI_FirstFPR,
537+
AArch64::PMI_FirstFPR};
534538
break;
535539
}
536540
case TargetOpcode::G_BITCAST: {
@@ -548,7 +552,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
548552
// for the greedy mode the cost of the cross bank copy will
549553
// offset this number.
550554
// FIXME: Should be derived from the scheduling model.
551-
if (OpRegBankIdx[0] >= AArch64::FirstFPR)
555+
if (OpRegBankIdx[0] >= AArch64::PMI_FirstFPR)
552556
Cost = 2;
553557
}
554558
}

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