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Commit a59d901

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Krzysztof Parzyszek
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[Hexagon] Add instruction aliases for vector unsigned compare-equal
Unsigned compare-equal instructions are mapped to signed compare-equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267925 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/Hexagon/HexagonAlias.td

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Original file line numberDiff line numberDiff line change
@@ -27,3 +27,68 @@ def : InstAlias<"$Vd = #0",
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def : InstAlias<"$Vdd = #0",
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(V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
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def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
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(V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
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Requires<[HasV60T]>;

‎test/MC/Hexagon/v60-misc.s

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Original file line numberDiff line numberDiff line change
@@ -8,3 +8,39 @@ v1:0 = #0
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# CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) }
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v1:0 = v3:2
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# CHECK: 1f90cf00 { q0 = vcmp.eq(v15.b,v16.b) }
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q0 = vcmp.eq(v15.ub, v16.ub)
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# CHECK: 1c92f101 { q1 &= vcmp.eq(v17.b,v18.b) }
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q1 &= vcmp.eq(v17.ub, v18.ub)
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# CHECK: 1c94f342 { q2 |= vcmp.eq(v19.b,v20.b) }
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q2 |= vcmp.eq(v19.ub, v20.ub)
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# CHECK: 1c96f583 { q3 ^= vcmp.eq(v21.b,v22.b) }
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q3 ^= vcmp.eq(v21.ub, v22.ub)
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# CHECK: 1f81c004 { q0 = vcmp.eq(v0.h,v1.h) }
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q0 = vcmp.eq(v0.uh, v1.uh)
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# CHECK: 1c83e205 { q1 &= vcmp.eq(v2.h,v3.h) }
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q1 &= vcmp.eq(v2.uh, v3.uh)
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# CHECK: 1c85e446 { q2 |= vcmp.eq(v4.h,v5.h) }
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q2 |= vcmp.eq(v4.uh, v5.uh)
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# CHECK: 1c87e687 { q3 ^= vcmp.eq(v6.h,v7.h) }
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q3 ^= vcmp.eq(v6.uh, v7.uh)
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# CHECK: 1f89c808 { q0 = vcmp.eq(v8.w,v9.w) }
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q0 = vcmp.eq(v8.uw, v9.uw)
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# CHECK: 1c8aea09 { q1 &= vcmp.eq(v10.w,v10.w) }
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q1 &= vcmp.eq(v10.uw, v10.uw)
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# CHECK: 1c8ceb46 { q2 |= vcmp.eq(v11.h,v12.h) }
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q2 |= vcmp.eq(v11.uw, v12.uw)
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# CHECK: 1c8eed8b { q3 ^= vcmp.eq(v13.w,v14.w) }
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q3 ^= vcmp.eq(v13.uw, v14.uw)

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