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[ARM] Add cdp intrinsic tests.
- Renamed intrinsics.ll to intrinsics-coprocessor.ll as all the tests were testing coprocessor instructions, also made the test checks match the full instruction. Differential Revision: http://reviews.llvm.org/D20393 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270057 91177308-0d34-0410-b5e6-96231b3b80d8
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test/CodeGen/ARM/cdp.ll

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; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp
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define void @cdp(i32 %a) #0 {
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%1 = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind

test/CodeGen/ARM/cdp2.ll

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; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2
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define void @cdp2(i32 %a) #0 {
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%1 = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind

test/CodeGen/ARM/intrinsics.ll renamed to test/CodeGen/ARM/intrinsics-coprocessor.ll

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define void @coproc() nounwind {
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entry:
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; CHECK: mrc
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; CHECK: mrc p7, #1, r0, c1, c1, #4
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%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr
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; CHECK: mcr p7, #1, r0, c1, c1, #4
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tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
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; CHECK: mrc2
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; CHECK: mrc2 p7, #1, r1, c1, c1, #4
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%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr2
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; CHECK: mcr2 p7, #1, r1, c1, c1, #4
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tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcrr
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; CHECK: mcrr p7, #1, r0, r1, c1
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tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: mcrr2
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; CHECK: mcrr2 p7, #1, r0, r1, c1
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tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: cdp
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; CHECK: cdp p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: cdp2
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; CHECK: cdp2 p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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ret void
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}

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