AArch64: match correct order in subtraction pattern.

The accumulator in multiply-and-subtract instructions is actually subtracted
*from* so these patterns were computing the wrong value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260131 91177308-0d34-0410-b5e6-96231b3b80d8

Author: TNorthover

lib/Target/AArch64/AArch64InstrInfo.td

@@ -766,12 +766,12 @@ def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),
           (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
                      (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
 
-def : Pat<(i64 (sub (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),
+def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
           (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
-def : Pat<(i64 (sub (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),
+def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
           (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
-def : Pat<(i64 (sub (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),
-                    GPR64:$Ra)),
+def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),
+                                    (s64imm_32bit:$C)))),
           (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
                      (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
 } // AddedComplexity = 5

test/CodeGen/AArch64/arm64-mul.ll

@@ -137,6 +137,16 @@ entry:
 ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
   %tmp1 = zext i32 %a to i64
   %tmp3 = mul i64 %tmp1, 12345678
-  %tmp4 = sub i64 %tmp3, %b
+  %tmp4 = sub i64 %b, %tmp3
+  ret i64 %tmp4
+}
+
+define i64 @t14(i32 %a, i64 %b) nounwind {
+entry:
+; CHECK-LABEL: t14:
+; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
+  %tmp1 = sext i32 %a to i64
+  %tmp3 = mul i64 %tmp1, -12345678
+  %tmp4 = sub i64 %b, %tmp3
   ret i64 %tmp4
 }